1f49714d3e
This diffs implements per-core tracing on lldb-server. It also includes tests that ensure that tracing can be initiated from the client and that the jLLDBGetState ppacket returns the list of trace buffers per core. This doesn't include any decoder changes. Finally, this makes some little changes here and there improving the existing code. A specific piece of code that can't reliably be tested is when tracing per core fails due to permissions. In this case we add a troubleshooting message and this is the manual test: ``` /proc/sys/kernel/perf_event_paranoid set to 1 (lldb) process trace start --per-core-tracing error: perf event syscall failed: Permission denied You might need that /proc/sys/kernel/perf_event_paranoid has a value of 0 or -1. `` Differential Revision: https://reviews.llvm.org/D124858
105 lines
2.8 KiB
C++
105 lines
2.8 KiB
C++
//===-- ProcfsTests.cpp ---------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "Procfs.h"
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#include "lldb/Host/linux/Support.h"
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#include "gmock/gmock.h"
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#include "gtest/gtest.h"
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using namespace lldb_private;
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using namespace process_linux;
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using namespace llvm;
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TEST(Perf, HardcodedLogicalCoreIDs) {
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Expected<std::vector<lldb::core_id_t>> core_ids =
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GetAvailableLogicalCoreIDs(R"(processor : 13
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vendor_id : GenuineIntel
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cpu family : 6
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model : 85
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model name : Intel(R) Xeon(R) Gold 6138 CPU @ 2.00GHz
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stepping : 4
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microcode : 0x2000065
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cpu MHz : 2886.370
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cache size : 28160 KB
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physical id : 1
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siblings : 40
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core id : 19
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cpu cores : 20
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apicid : 103
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initial apicid : 103
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fpu : yes
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fpu_exception : yes
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cpuid level : 22
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power management:
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processor : 24
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vendor_id : GenuineIntel
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cpu family : 6
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model : 85
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model name : Intel(R) Xeon(R) Gold 6138 CPU @ 2.00GHz
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stepping : 4
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microcode : 0x2000065
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cpu MHz : 2768.494
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cache size : 28160 KB
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physical id : 1
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siblings : 40
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core id : 20
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cpu cores : 20
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apicid : 105
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power management:
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processor : 35
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vendor_id : GenuineIntel
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cpu family : 6
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model : 85
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model name : Intel(R) Xeon(R) Gold 6138 CPU @ 2.00GHz
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stepping : 4
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microcode : 0x2000065
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cpu MHz : 2884.703
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cache size : 28160 KB
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physical id : 1
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siblings : 40
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core id : 24
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cpu cores : 20
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apicid : 113
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processor : 79
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vendor_id : GenuineIntel
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cpu family : 6
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model : 85
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model name : Intel(R) Xeon(R) Gold 6138 CPU @ 2.00GHz
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stepping : 4
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microcode : 0x2000065
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cpu MHz : 3073.955
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cache size : 28160 KB
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physical id : 1
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siblings : 40
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core id : 28
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cpu cores : 20
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apicid : 121
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power management:
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)");
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ASSERT_TRUE((bool)core_ids);
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ASSERT_THAT(*core_ids, ::testing::ElementsAre(13, 24, 35, 79));
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}
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TEST(Perf, RealLogicalCoreIDs) {
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// We first check we can read /proc/cpuinfo
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auto buffer_or_error = errorOrToExpected(getProcFile("cpuinfo"));
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if (!buffer_or_error)
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GTEST_SKIP() << toString(buffer_or_error.takeError());
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// At this point we shouldn't fail parsing the core ids
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Expected<ArrayRef<lldb::core_id_t>> core_ids = GetAvailableLogicalCoreIDs();
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ASSERT_TRUE((bool)core_ids);
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ASSERT_GT((int)core_ids->size(), 0) << "We must see at least one core";
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}
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