e243ead6fc
There was an issue with encoding wide (>64 bit) instructions on BigEndian hosts, which is fixed in D127195. Therefore reland this. gfx11 adds the ability to use dpp modifiers on vop3 instructions. This patch adds machine code layer support for that. The MCCodeEmitter is changed to use APInt instead of uint64_t to support these wider instructions. Patch 16/N for upstreaming of AMDGPU gfx11 architecture Differential Revision: https://reviews.llvm.org/D126483
77 lines
2.8 KiB
C++
77 lines
2.8 KiB
C++
//===-- AMDGPUCodeEmitter.h - AMDGPU Code Emitter interface -----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// CodeEmitter interface for SI codegen.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCCODEEMITTER_H
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#define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCCODEEMITTER_H
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#include "llvm/ADT/APInt.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include <cstdint>
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namespace llvm {
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class MCInst;
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class MCInstrInfo;
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class MCOperand;
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class MCSubtargetInfo;
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class FeatureBitset;
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class AMDGPUMCCodeEmitter : public MCCodeEmitter {
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virtual void anchor();
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protected:
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const MCInstrInfo &MCII;
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AMDGPUMCCodeEmitter(const MCInstrInfo &mcii) : MCII(mcii) {}
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public:
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void getBinaryCodeForInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
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APInt &Inst, APInt &Scratch,
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const MCSubtargetInfo &STI) const;
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virtual void getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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APInt &Op, SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const = 0;
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virtual void getSOPPBrEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const = 0;
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virtual void getSMEMOffsetEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const = 0;
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virtual void getSDWASrcEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const = 0;
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virtual void getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo,
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APInt &Op,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const = 0;
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virtual void getAVOperandEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const = 0;
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protected:
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FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) const;
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void
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verifyInstructionPredicates(const MCInst &MI,
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const FeatureBitset &AvailableFeatures) const;
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};
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} // End namespace llvm
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#endif
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