407b613d73
Integer materializing can generate LU12I_W, ORI, LU32I_D, LU52I_D and ADDI_W instructions. According to the sign-extended behavior of these instructions (except ORI), the generated instruction sequence can be improved. For example, load -1 into general register: The ADDI_W instruction performs the operation that the [31:0] bit data in the general register `rj` plus the 12-bit immediate `simm12` sign extension 32-bit data; the resultant [31:0] bit is sign extension, then written into the general register `rd`. Normal sequence: ``` lu12i.w $a0, -1 ori $a0, $a0, 2048 ``` Improved with sign-extended instruction: ``` addi.w $a0, $zero, -1 ``` Reviewed By: SixWeining, MaskRay Differential Revision: https://reviews.llvm.org/D123290
67 lines
2.2 KiB
C++
67 lines
2.2 KiB
C++
//=- LoongArchISelDAGToDAG.cpp - A dag to dag inst selector for LoongArch -===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the LoongArch target.
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//
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//===----------------------------------------------------------------------===//
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#include "LoongArchISelDAGToDAG.h"
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#include "MCTargetDesc/LoongArchMCTargetDesc.h"
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#include "MCTargetDesc/LoongArchMatInt.h"
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using namespace llvm;
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#define DEBUG_TYPE "loongarch-isel"
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void LoongArchDAGToDAGISel::Select(SDNode *Node) {
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// If we have a custom node, we have already selected.
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if (Node->isMachineOpcode()) {
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LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");
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Node->setNodeId(-1);
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return;
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}
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// Instruction Selection not handled by the auto-generated tablegen selection
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// should be handled here.
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unsigned Opcode = Node->getOpcode();
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MVT GRLenVT = Subtarget->getGRLenVT();
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SDLoc DL(Node);
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switch (Opcode) {
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default:
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break;
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case ISD::Constant: {
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int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
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SDNode *Result = nullptr;
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SDValue SrcReg = CurDAG->getRegister(LoongArch::R0, GRLenVT);
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// The instructions in the sequence are handled here.
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for (LoongArchMatInt::Inst &Inst : LoongArchMatInt::generateInstSeq(Imm)) {
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SDValue SDImm = CurDAG->getTargetConstant(Inst.Imm, DL, GRLenVT);
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if (Inst.Opc == LoongArch::LU12I_W)
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Result = CurDAG->getMachineNode(LoongArch::LU12I_W, DL, GRLenVT, SDImm);
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else
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Result = CurDAG->getMachineNode(Inst.Opc, DL, GRLenVT, SrcReg, SDImm);
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SrcReg = SDValue(Result, 0);
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}
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ReplaceNode(Node, Result);
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return;
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}
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// TODO: Add selection nodes needed later.
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}
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// Select the default instruction.
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SelectCode(Node);
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}
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// This pass converts a legalized DAG into a LoongArch-specific DAG, ready
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// for instruction scheduling.
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FunctionPass *llvm::createLoongArchISelDag(LoongArchTargetMachine &TM) {
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return new LoongArchDAGToDAGISel(TM);
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}
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