0098f2aebb
The patch adds SPIR-V specific intrinsics required to keep information critical to SPIR-V consistency (types, constants, etc.) during translation from IR to MIR. Two related passes (SPIRVEmitIntrinsics and SPIRVPreLegalizer) and several LIT tests (passed with this change) have also been added. It also fixes the issue with opaque pointers in SPIRVGlobalRegistry.cpp and the mismatch of the data layout between the SPIR-V backend and clang (Issue #55122). Differential Revision: https://reviews.llvm.org/D124416 Co-authored-by: Aleksandr Bezzubikov <zuban32s@gmail.com> Co-authored-by: Michal Paszkowski <michal.paszkowski@outlook.com> Co-authored-by: Andrey Tretyakov <andrey1.tretyakov@intel.com> Co-authored-by: Konrad Trifunovic <konrad.trifunovic@intel.com>
84 lines
3.3 KiB
C++
84 lines
3.3 KiB
C++
//===--- SPIRVUtils.h ---- SPIR-V Utility Functions -------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains miscellaneous utility functions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_SPIRV_SPIRVUTILS_H
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#define LLVM_LIB_TARGET_SPIRV_SPIRVUTILS_H
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#include "MCTargetDesc/SPIRVBaseInfo.h"
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#include "llvm/IR/IRBuilder.h"
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#include <string>
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namespace llvm {
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class MCInst;
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class MachineFunction;
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class MachineInstr;
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class MachineInstrBuilder;
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class MachineIRBuilder;
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class MachineRegisterInfo;
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class Register;
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class StringRef;
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class SPIRVInstrInfo;
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} // namespace llvm
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// Add the given string as a series of integer operand, inserting null
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// terminators and padding to make sure the operands all have 32-bit
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// little-endian words.
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void addStringImm(const llvm::StringRef &Str, llvm::MachineInstrBuilder &MIB);
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void addStringImm(const llvm::StringRef &Str, llvm::IRBuilder<> &B,
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std::vector<llvm::Value *> &Args);
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// Read the series of integer operands back as a null-terminated string using
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// the reverse of the logic in addStringImm.
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std::string getStringImm(const llvm::MachineInstr &MI, unsigned StartIndex);
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// Add the given numerical immediate to MIB.
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void addNumImm(const llvm::APInt &Imm, llvm::MachineInstrBuilder &MIB);
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// Add an OpName instruction for the given target register.
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void buildOpName(llvm::Register Target, const llvm::StringRef &Name,
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llvm::MachineIRBuilder &MIRBuilder);
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// Add an OpDecorate instruction for the given Reg.
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void buildOpDecorate(llvm::Register Reg, llvm::MachineIRBuilder &MIRBuilder,
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llvm::SPIRV::Decoration Dec,
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const std::vector<uint32_t> &DecArgs,
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llvm::StringRef StrImm = "");
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void buildOpDecorate(llvm::Register Reg, llvm::MachineInstr &I,
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const llvm::SPIRVInstrInfo &TII,
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llvm::SPIRV::Decoration Dec,
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const std::vector<uint32_t> &DecArgs,
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llvm::StringRef StrImm = "");
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// Convert a SPIR-V storage class to the corresponding LLVM IR address space.
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unsigned storageClassToAddressSpace(llvm::SPIRV::StorageClass SC);
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// Convert an LLVM IR address space to a SPIR-V storage class.
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llvm::SPIRV::StorageClass addressSpaceToStorageClass(unsigned AddrSpace);
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llvm::SPIRV::MemorySemantics
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getMemSemanticsForStorageClass(llvm::SPIRV::StorageClass SC);
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// Find def instruction for the given ConstReg, walking through
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// spv_track_constant and ASSIGN_TYPE instructions. Updates ConstReg by def
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// of OpConstant instruction.
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llvm::MachineInstr *
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getDefInstrMaybeConstant(llvm::Register &ConstReg,
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const llvm::MachineRegisterInfo *MRI);
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// Get constant integer value of the given ConstReg.
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uint64_t getIConstVal(llvm::Register ConstReg,
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const llvm::MachineRegisterInfo *MRI);
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// Get type of i-th operand of the metadata node.
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llvm::Type *getMDOperandAsType(const llvm::MDNode *N, unsigned I);
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#endif // LLVM_LIB_TARGET_SPIRV_SPIRVUTILS_H
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