18ed279a3a
Tablegen definitions for subtarget features and cpp predicate functions to access the features. New Sub-TargetProcessors and common latencies. Simple changes to MIR codegen tests which pass on gfx11 because they have the same output as previous subtargets or operate on pseudo instructions which are reused from previous subtargets. Contributors: Jay Foad <jay.foad@amd.com> Petar Avramovic <Petar.Avramovic@amd.com> Patch 4/N for upstreaming of AMDGPU gfx11 architecture Depends on D124538 Reviewed By: Petar.Avramovic, foad Differential Revision: https://reviews.llvm.org/D125261
89 lines
4.7 KiB
YAML
89 lines
4.7 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
|
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=WAVE64 %s
|
|
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=WAVE64 %s
|
|
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=WAVE64 %s
|
|
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=WAVE32 %s
|
|
# RUN: llc -march=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=WAVE32 %s
|
|
|
|
---
|
|
name: uadde_s32_s1_sss
|
|
legalized: true
|
|
regBankSelected: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $sgpr0, $sgpr1, $sgpr2
|
|
|
|
; WAVE64-LABEL: name: uadde_s32_s1_sss
|
|
; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
|
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
|
; WAVE64: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
|
|
; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
|
; WAVE64: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
|
|
; WAVE64: [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
|
|
; WAVE64: $scc = COPY [[COPY3]]
|
|
; WAVE64: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY]], [[COPY1]], implicit-def $scc, implicit $scc
|
|
; WAVE64: [[COPY4:%[0-9]+]]:sreg_32 = COPY $scc
|
|
; WAVE64: $scc = COPY [[COPY4]]
|
|
; WAVE64: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc
|
|
; WAVE64: S_ENDPGM 0, implicit [[S_ADDC_U32_]], implicit [[S_CSELECT_B32_]]
|
|
; WAVE32-LABEL: name: uadde_s32_s1_sss
|
|
; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
|
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
|
; WAVE32: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
|
|
; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
|
; WAVE32: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
|
|
; WAVE32: [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
|
|
; WAVE32: $scc = COPY [[COPY3]]
|
|
; WAVE32: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY]], [[COPY1]], implicit-def $scc, implicit $scc
|
|
; WAVE32: [[COPY4:%[0-9]+]]:sreg_32 = COPY $scc
|
|
; WAVE32: $scc = COPY [[COPY4]]
|
|
; WAVE32: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc
|
|
; WAVE32: S_ENDPGM 0, implicit [[S_ADDC_U32_]], implicit [[S_CSELECT_B32_]]
|
|
%0:sgpr(s32) = COPY $sgpr0
|
|
%1:sgpr(s32) = COPY $sgpr1
|
|
%2:sgpr(s32) = COPY $sgpr2
|
|
%3:sgpr(s32) = G_CONSTANT i32 0
|
|
%4:sgpr(s32) = G_ICMP intpred(eq), %2, %3
|
|
%5:sgpr(s32), %6:sgpr(s32) = G_UADDE %0, %1, %4
|
|
%7:sgpr(s32) = G_SELECT %6, %0, %1
|
|
S_ENDPGM 0, implicit %5, implicit %7
|
|
...
|
|
|
|
---
|
|
name: uadde_s32_s1_vvv
|
|
legalized: true
|
|
regBankSelected: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0, $vgpr1, $vgpr2
|
|
|
|
; WAVE64-LABEL: name: uadde_s32_s1_vvv
|
|
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
|
; WAVE64: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
|
; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
|
; WAVE64: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY2]], [[V_MOV_B32_e32_]], implicit $exec
|
|
; WAVE64: [[V_ADDC_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADDC_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADDC_U32_e64 [[COPY]], [[COPY1]], [[V_CMP_EQ_U32_e64_]], 0, implicit $exec
|
|
; WAVE64: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY1]], 0, [[COPY]], [[V_ADDC_U32_e64_1]], implicit $exec
|
|
; WAVE64: S_ENDPGM 0, implicit [[V_ADDC_U32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
|
|
; WAVE32-LABEL: name: uadde_s32_s1_vvv
|
|
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
|
; WAVE32: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
|
; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
|
; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY2]], [[V_MOV_B32_e32_]], implicit $exec
|
|
; WAVE32: [[V_ADDC_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADDC_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_ADDC_U32_e64 [[COPY]], [[COPY1]], [[V_CMP_EQ_U32_e64_]], 0, implicit $exec
|
|
; WAVE32: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY1]], 0, [[COPY]], [[V_ADDC_U32_e64_1]], implicit $exec
|
|
; WAVE32: S_ENDPGM 0, implicit [[V_ADDC_U32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
|
|
%0:vgpr(s32) = COPY $vgpr0
|
|
%1:vgpr(s32) = COPY $vgpr1
|
|
%2:vgpr(s32) = COPY $vgpr2
|
|
%3:vgpr(s32) = G_CONSTANT i32 0
|
|
%4:vcc(s1) = G_ICMP intpred(eq), %2, %3
|
|
%5:vgpr(s32), %6:vcc(s1) = G_UADDE %0, %1, %4
|
|
%7:vgpr(s32) = G_SELECT %6, %0, %1
|
|
S_ENDPGM 0, implicit %5, implicit %7
|
|
...
|