18ed279a3a
Tablegen definitions for subtarget features and cpp predicate functions to access the features. New Sub-TargetProcessors and common latencies. Simple changes to MIR codegen tests which pass on gfx11 because they have the same output as previous subtargets or operate on pseudo instructions which are reused from previous subtargets. Contributors: Jay Foad <jay.foad@amd.com> Petar Avramovic <Petar.Avramovic@amd.com> Patch 4/N for upstreaming of AMDGPU gfx11 architecture Depends on D124538 Reviewed By: Petar.Avramovic, foad Differential Revision: https://reviews.llvm.org/D125261
119 lines
4.4 KiB
YAML
119 lines
4.4 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GFX9 %s
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# RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=VI %s
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# RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=CI %s
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# RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=SI %s
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# RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GFX10 %s
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# RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GFX10 %s
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---
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name: m0_gws_init0
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GFX9-LABEL: name: m0_gws_init0
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; GFX9: liveins: $vgpr0
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; GFX9: $m0 = S_MOV_B32 -1
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; GFX9: S_NOP 0
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; GFX9: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
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; VI-LABEL: name: m0_gws_init0
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; VI: liveins: $vgpr0
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; VI: $m0 = S_MOV_B32 -1
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; VI: S_NOP 0
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; VI: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
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; CI-LABEL: name: m0_gws_init0
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; CI: liveins: $vgpr0
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; CI: $m0 = S_MOV_B32 -1
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; CI: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
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; SI-LABEL: name: m0_gws_init0
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; SI: liveins: $vgpr0
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; SI: $m0 = S_MOV_B32 -1
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; SI: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
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; GFX10-LABEL: name: m0_gws_init0
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; GFX10: liveins: $vgpr0
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; GFX10: $m0 = S_MOV_B32 -1
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; GFX10: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
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$m0 = S_MOV_B32 -1
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DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
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...
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---
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name: m0_gws_init1
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tracksRegLiveness: true
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body: |
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bb.0:
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; GFX9-LABEL: name: m0_gws_init1
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; GFX9: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
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; GFX9: $m0 = S_MOV_B32 -1
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; GFX9: S_NOP 0
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; GFX9: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
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; VI-LABEL: name: m0_gws_init1
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; VI: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
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; VI: $m0 = S_MOV_B32 -1
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; VI: S_NOP 0
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; VI: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
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; CI-LABEL: name: m0_gws_init1
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; CI: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
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; CI: $m0 = S_MOV_B32 -1
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; CI: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
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; SI-LABEL: name: m0_gws_init1
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; SI: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
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; SI: $m0 = S_MOV_B32 -1
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; SI: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
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; GFX10-LABEL: name: m0_gws_init1
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; GFX10: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
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; GFX10: $m0 = S_MOV_B32 -1
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; GFX10: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
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$vgpr0 = V_MOV_B32_e32 0, implicit $exec
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$m0 = S_MOV_B32 -1
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DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
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...
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# Test a typical situation where m0 needs to be set from a VGPR
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# through readfirstlane
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---
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name: m0_gws_readlane
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX9-LABEL: name: m0_gws_readlane
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; GFX9: liveins: $vgpr0, $vgpr1
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; GFX9: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
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; GFX9: $m0 = S_MOV_B32 $sgpr0
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; GFX9: S_NOP 0
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; GFX9: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
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; VI-LABEL: name: m0_gws_readlane
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; VI: liveins: $vgpr0, $vgpr1
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; VI: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
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; VI: $m0 = S_MOV_B32 $sgpr0
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; VI: S_NOP 0
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; VI: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
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; CI-LABEL: name: m0_gws_readlane
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; CI: liveins: $vgpr0, $vgpr1
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; CI: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
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; CI: $m0 = S_MOV_B32 $sgpr0
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; CI: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
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; SI-LABEL: name: m0_gws_readlane
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; SI: liveins: $vgpr0, $vgpr1
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; SI: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
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; SI: $m0 = S_MOV_B32 $sgpr0
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; SI: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
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; GFX10-LABEL: name: m0_gws_readlane
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; GFX10: liveins: $vgpr0, $vgpr1
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; GFX10: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
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; GFX10: $m0 = S_MOV_B32 $sgpr0
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; GFX10: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
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$sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
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$m0 = S_MOV_B32 $sgpr0
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DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
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...
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