18ed279a3a
Tablegen definitions for subtarget features and cpp predicate functions to access the features. New Sub-TargetProcessors and common latencies. Simple changes to MIR codegen tests which pass on gfx11 because they have the same output as previous subtargets or operate on pseudo instructions which are reused from previous subtargets. Contributors: Jay Foad <jay.foad@amd.com> Petar Avramovic <Petar.Avramovic@amd.com> Patch 4/N for upstreaming of AMDGPU gfx11 architecture Depends on D124538 Reviewed By: Petar.Avramovic, foad Differential Revision: https://reviews.llvm.org/D125261
118 lines
4.6 KiB
YAML
118 lines
4.6 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -run-pass=machine-cse -o - %s | FileCheck %s
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -run-pass=machine-cse -o - %s | FileCheck %s
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--- |
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define void @commute_instruction_subreg_target_flag() { ret void }
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define void @commute_target_flag_frame_index() { ret void }
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define void @commute_target_flag_global() { ret void }
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define void @commute_target_flag_global_offset() { ret void }
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define void @commute_target_flag_global_offset_mismatch() { ret void }
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declare void @func()
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@gv = external addrspace(1) global i32
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...
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# Make sure the subreg index is cleared when commuting a register and immediate.
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---
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name: commute_instruction_subreg_target_flag
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: commute_instruction_subreg_target_flag
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; CHECK: liveins: $vgpr0_vgpr1
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; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; CHECK: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]].sub1, 64, 0, implicit $exec
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; CHECK: S_ENDPGM 0, implicit [[V_ADD_U32_e64_]], implicit [[V_ADD_U32_e64_]]
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%0:vreg_64 = COPY $vgpr0_vgpr1
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%1:vgpr_32 = V_ADD_U32_e64 %0.sub1, 64, 0, implicit $exec
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%2:vgpr_32 = V_ADD_U32_e64 64, %0.sub1, 0, implicit $exec
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S_ENDPGM 0, implicit %1, implicit %2
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...
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# FIXME: Why doesn't this CSE?
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---
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name: commute_target_flag_frame_index
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tracksRegLiveness: true
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stack:
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- { id: 0, type: default, offset: 0, size: 4, alignment: 4 }
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: commute_target_flag_frame_index
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; CHECK: liveins: $vgpr0_vgpr1
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; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; CHECK: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %stack.0, [[COPY]].sub0, 0, implicit $exec
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; CHECK: S_ENDPGM 0, implicit [[V_ADD_U32_e64_]], implicit [[V_ADD_U32_e64_]]
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%0:vreg_64 = COPY $vgpr0_vgpr1
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%1:vgpr_32 = V_ADD_U32_e64 %0.sub0, %stack.0, 0, implicit $exec
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%2:vgpr_32 = V_ADD_U32_e64 %stack.0, %0.sub0, 0, implicit $exec
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S_ENDPGM 0, implicit %1, implicit %2
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...
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# FIXME: Handle commuting global variables
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---
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name: commute_target_flag_global
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; CHECK-LABEL: name: commute_target_flag_global
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; CHECK: liveins: $sgpr0_sgpr1
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; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; CHECK: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]].sub0, target-flags(amdgpu-rel32-lo) @func, implicit-def dead $scc
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; CHECK: S_ENDPGM 0, implicit [[S_ADD_U32_]], implicit [[S_ADD_U32_]]
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%0:sreg_64 = COPY $sgpr0_sgpr1
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%1:sreg_32 = S_ADD_U32 %0.sub0, target-flags(amdgpu-rel32-lo) @func, implicit-def dead $scc
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%2:sreg_32 = S_ADD_U32 target-flags(amdgpu-rel32-lo) @func, %0.sub0, implicit-def dead $scc
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S_ENDPGM 0, implicit %1, implicit %2
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...
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---
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name: commute_target_flag_global_offset
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; CHECK-LABEL: name: commute_target_flag_global_offset
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; CHECK: liveins: $sgpr0_sgpr1
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; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; CHECK: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]].sub0, target-flags(amdgpu-rel32-lo) @gv + 4, implicit-def dead $scc
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; CHECK: S_ENDPGM 0, implicit [[S_ADD_U32_]], implicit [[S_ADD_U32_]]
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%0:sreg_64 = COPY $sgpr0_sgpr1
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%1:sreg_32 = S_ADD_U32 %0.sub0, target-flags(amdgpu-rel32-lo) @gv + 4, implicit-def dead $scc
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%2:sreg_32 = S_ADD_U32 target-flags(amdgpu-rel32-lo) @gv + 4, %0.sub0, implicit-def dead $scc
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S_ENDPGM 0, implicit %1, implicit %2
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...
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---
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name: commute_target_flag_global_offset_mismatch
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; CHECK-LABEL: name: commute_target_flag_global_offset_mismatch
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; CHECK: liveins: $sgpr0_sgpr1
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; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; CHECK: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]].sub0, target-flags(amdgpu-rel32-lo) @gv + 4, implicit-def dead $scc
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; CHECK: [[S_ADD_U32_1:%[0-9]+]]:sreg_32 = S_ADD_U32 target-flags(amdgpu-rel32-lo) @gv + 8, [[COPY]].sub0, implicit-def dead $scc
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; CHECK: S_ENDPGM 0, implicit [[S_ADD_U32_]], implicit [[S_ADD_U32_1]]
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%0:sreg_64 = COPY $sgpr0_sgpr1
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%1:sreg_32 = S_ADD_U32 %0.sub0, target-flags(amdgpu-rel32-lo) @gv + 4, implicit-def dead $scc
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%2:sreg_32 = S_ADD_U32 target-flags(amdgpu-rel32-lo) @gv + 8, %0.sub0, implicit-def dead $scc
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S_ENDPGM 0, implicit %1, implicit %2
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...
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