23 lines
772 B
LLVM
23 lines
772 B
LLVM
; RUN: llc -march=hexagon -no-integrated-as < %s | FileCheck %s
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; Check that constraints q and v are handled correctly.
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; CHECK: q{{.}} = vgtw(v{{.}}.w,v{{.}}.w)
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; CHECK: vand
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; CHECK: vmem
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target triple = "hexagon"
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; Function Attrs: nounwind
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define void @foo(<16 x i32> %v0, <16 x i32> %v1, <16 x i32>* nocapture %p) #0 {
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entry:
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%0 = tail call <64 x i1> asm "$0 = vgtw($1.w,$2.w)", "=q,v,v"(<16 x i32> %v0, <16 x i32> %v1) #1
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%1 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %0, i32 -1) #1
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store <16 x i32> %1, <16 x i32>* %p, align 64
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ret void
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}
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declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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