d65fa2c43c
Such vector types cannot be split at the moment, because splitting expects an even number of elements in the source type. If a target marks such a type as "split", TargetLoweringBase::computeRegisterProperties will override it with widening to the next power of 2. This could lead to issues during instruction selection when conflicting information about how to handle this type is present.
41 lines
1.4 KiB
LLVM
41 lines
1.4 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; Check for a successful compilation.
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; CHECK: callr
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target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
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target triple = "hexagon"
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@g0 = external dllexport global i8* (i32, i32, i64, i32, i32)*, align 4
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define hidden void @f0(i32 %a0, <3 x i16>* %a1) #0 {
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b0:
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%v0 = load i8* (i32, i32, i64, i32, i32)*, i8* (i32, i32, i64, i32, i32)** @g0, align 4
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%v1 = call i8* %v0(i32 1, i32 %a0, i64 314646, i32 0, i32 16)
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br label %b1
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b1: ; preds = %b2, %b0
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br label %b2
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b2: ; preds = %b5, %b1
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%v2 = icmp slt i32 0, 229
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br i1 %v2, label %b3, label %b1
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b3: ; preds = %b2
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br i1 undef, label %b4, label %b5
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b4: ; preds = %b3
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%v3 = load <3 x i16>, <3 x i16>* %a1, align 2
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br label %b5
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b5: ; preds = %b4, %b3
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%v4 = phi <3 x i16> [ %v3, %b4 ], [ zeroinitializer, %b3 ]
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%v5 = bitcast i8* %v1 to i16*
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%v6 = getelementptr inbounds i16, i16* %v5, i32 undef
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%v7 = bitcast i16* %v6 to <3 x i16>*
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store <3 x i16> %v4, <3 x i16>* %v7, align 2
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br label %b2
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}
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attributes #0 = { "target-cpu"="hexagonv68" }
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