407b613d73
Integer materializing can generate LU12I_W, ORI, LU32I_D, LU52I_D and ADDI_W instructions. According to the sign-extended behavior of these instructions (except ORI), the generated instruction sequence can be improved. For example, load -1 into general register: The ADDI_W instruction performs the operation that the [31:0] bit data in the general register `rj` plus the 12-bit immediate `simm12` sign extension 32-bit data; the resultant [31:0] bit is sign extension, then written into the general register `rd`. Normal sequence: ``` lu12i.w $a0, -1 ori $a0, $a0, 2048 ``` Improved with sign-extended instruction: ``` addi.w $a0, $zero, -1 ``` Reviewed By: SixWeining, MaskRay Differential Revision: https://reviews.llvm.org/D123290
158 lines
4.1 KiB
LLVM
158 lines
4.1 KiB
LLVM
; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
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define i64 @imm7ff0000000000000() {
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; CHECK-LABEL: imm7ff0000000000000:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lu52i.d $a0, $zero, 2047
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; CHECK-NEXT: jirl $zero, $ra, 0
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ret i64 9218868437227405312
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}
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define i64 @imm0000000000000fff() {
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; CHECK-LABEL: imm0000000000000fff:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ori $a0, $zero, 4095
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; CHECK-NEXT: jirl $zero, $ra, 0
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ret i64 4095
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}
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define i64 @imm0007ffff00000800() {
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; CHECK-LABEL: imm0007ffff00000800:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ori $a0, $zero, 2048
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; CHECK-NEXT: lu32i.d $a0, 524287
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; CHECK-NEXT: jirl $zero, $ra, 0
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ret i64 2251795518720000
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}
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define i64 @immfff0000000000fff() {
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; CHECK-LABEL: immfff0000000000fff:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ori $a0, $zero, 4095
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; CHECK-NEXT: lu52i.d $a0, $a0, -1
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; CHECK-NEXT: jirl $zero, $ra, 0
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ret i64 -4503599627366401
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}
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define i64 @imm0008000000000fff() {
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; CHECK-LABEL: imm0008000000000fff:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ori $a0, $zero, 4095
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; CHECK-NEXT: lu32i.d $a0, -524288
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; CHECK-NEXT: lu52i.d $a0, $a0, 0
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; CHECK-NEXT: jirl $zero, $ra, 0
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ret i64 2251799813689343
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}
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define i64 @immfffffffffffff800() {
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; CHECK-LABEL: immfffffffffffff800:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi.w $a0, $zero, -2048
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; CHECK-NEXT: jirl $zero, $ra, 0
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ret i64 -2048
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}
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define i64 @imm00000000fffff800() {
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; CHECK-LABEL: imm00000000fffff800:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi.w $a0, $zero, -2048
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; CHECK-NEXT: lu32i.d $a0, 0
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; CHECK-NEXT: jirl $zero, $ra, 0
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ret i64 4294965248
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}
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define i64 @imm000ffffffffff800() {
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; CHECK-LABEL: imm000ffffffffff800:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi.w $a0, $zero, -2048
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; CHECK-NEXT: lu52i.d $a0, $a0, 0
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; CHECK-NEXT: jirl $zero, $ra, 0
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ret i64 4503599627368448
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}
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define i64 @imm00080000fffff800() {
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; CHECK-LABEL: imm00080000fffff800:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi.w $a0, $zero, -2048
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; CHECK-NEXT: lu32i.d $a0, -524288
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; CHECK-NEXT: lu52i.d $a0, $a0, 0
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; CHECK-NEXT: jirl $zero, $ra, 0
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ret i64 2251804108650496
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}
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define i64 @imm000000007ffff000() {
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; CHECK-LABEL: imm000000007ffff000:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lu12i.w $a0, 524287
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; CHECK-NEXT: jirl $zero, $ra, 0
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ret i64 2147479552
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}
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define i64 @imm0000000080000000() {
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; CHECK-LABEL: imm0000000080000000:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lu12i.w $a0, -524288
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; CHECK-NEXT: lu32i.d $a0, 0
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; CHECK-NEXT: jirl $zero, $ra, 0
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ret i64 2147483648
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}
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define i64 @imm000ffffffffff000() {
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; CHECK-LABEL: imm000ffffffffff000:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lu12i.w $a0, -1
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; CHECK-NEXT: lu52i.d $a0, $a0, 0
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; CHECK-NEXT: jirl $zero, $ra, 0
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ret i64 4503599627366400
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}
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define i64 @imm7ff0000080000000() {
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; CHECK-LABEL: imm7ff0000080000000:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lu12i.w $a0, -524288
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; CHECK-NEXT: lu32i.d $a0, 0
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; CHECK-NEXT: lu52i.d $a0, $a0, 2047
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; CHECK-NEXT: jirl $zero, $ra, 0
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ret i64 9218868439374888960
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}
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define i64 @immffffffff80000800() {
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; CHECK-LABEL: immffffffff80000800:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lu12i.w $a0, -524288
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; CHECK-NEXT: ori $a0, $a0, 2048
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; CHECK-NEXT: jirl $zero, $ra, 0
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ret i64 -2147481600
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}
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define i64 @immffffffff7ffff800() {
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; CHECK-LABEL: immffffffff7ffff800:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lu12i.w $a0, 524287
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; CHECK-NEXT: ori $a0, $a0, 2048
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; CHECK-NEXT: lu32i.d $a0, -1
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; CHECK-NEXT: jirl $zero, $ra, 0
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ret i64 -2147485696
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}
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define i64 @imm7fffffff800007ff() {
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; CHECK-LABEL: imm7fffffff800007ff:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lu12i.w $a0, -524288
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; CHECK-NEXT: ori $a0, $a0, 2047
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; CHECK-NEXT: lu52i.d $a0, $a0, 2047
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; CHECK-NEXT: jirl $zero, $ra, 0
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ret i64 9223372034707294207
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}
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define i64 @imm0008000080000800() {
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; CHECK-LABEL: imm0008000080000800:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lu12i.w $a0, -524288
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; CHECK-NEXT: ori $a0, $a0, 2048
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; CHECK-NEXT: lu32i.d $a0, -524288
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; CHECK-NEXT: lu52i.d $a0, $a0, 0
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; CHECK-NEXT: jirl $zero, $ra, 0
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ret i64 2251801961170944
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}
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