0f1b5f115a
ptxas is a proprietary compiler from Nvidia that can compile PTX to machine code (SASS). It has a lot of diagnostics to catch errors in PTX, which can be used to verify PTX output from llc. Set -DPXTAS_EXECUTABLE=/path/to/ptxas CMake option to enable it. If this option is not set, then ptxas is substituted to true which effectively disables all ptxas RUN lines. LLVM_PTXAS_EXECUTABLE environment variable takes precedence over the CMake option, and allows to override ptxas executable that is used for LIT without complete re-configuration. Differential Revision: https://reviews.llvm.org/D121727
60 lines
2.5 KiB
LLVM
60 lines
2.5 KiB
LLVM
; RUN: llc < %s -O0 -march=nvptx -mcpu=sm_20 | FileCheck %s
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; RUN: %if ptxas %{ llc < %s -O0 -march=nvptx -mcpu=sm_20 | %ptxas-verify %}
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; CHECK-LABEL: .visible .func callee(
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; CHECK-NEXT: .param .align 16 .b8 callee_param_0[16],
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; CHECK-NEXT: .param .align 16 .b8 callee_param_1[16],
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define void @callee(i128, i128, i128*) {
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; CHECK-DAG: ld.param.v2.u64 {%[[REG0:rd[0-9]+]], %[[REG1:rd[0-9]+]]}, [callee_param_0];
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; CHECK-DAG: ld.param.v2.u64 {%[[REG2:rd[0-9]+]], %[[REG3:rd[0-9]+]]}, [callee_param_1];
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; CHECK: mul.lo.s64 %[[REG4:rd[0-9]+]], %[[REG0]], %[[REG3]];
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; CHECK-NEXT: mul.hi.u64 %[[REG5:rd[0-9]+]], %[[REG0]], %[[REG2]];
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; CHECK-NEXT: add.s64 %[[REG6:rd[0-9]+]], %[[REG5]], %[[REG4]];
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; CHECK-NEXT: mul.lo.s64 %[[REG7:rd[0-9]+]], %[[REG1]], %[[REG2]];
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; CHECK-NEXT: add.s64 %[[REG8:rd[0-9]+]], %[[REG6]], %[[REG7]];
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; CHECK-NEXT: mul.lo.s64 %[[REG9:rd[0-9]+]], %[[REG0]], %[[REG2]];
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%a = mul i128 %0, %1
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store i128 %a, i128* %2
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ret void
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}
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; CHECK-LABEL: .visible .entry caller_kernel(
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; CHECK-NEXT: .param .align 16 .b8 caller_kernel_param_0[16],
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; CHECK-NEXT: .param .align 16 .b8 caller_kernel_param_1[16],
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define ptx_kernel void @caller_kernel(i128, i128, i128*) {
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start:
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; CHECK-DAG: ld.param.v2.u64 {%[[REG0:rd[0-9]+]], %[[REG1:rd[0-9]+]]}, [caller_kernel_param_0];
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; CHECK-DAG: ld.param.v2.u64 {%[[REG2:rd[0-9]+]], %[[REG3:rd[0-9]+]]}, [caller_kernel_param_1];
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; CHECK: { // callseq [[CALLSEQ_ID:[0-9]]], 0
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; CHECK: .param .align 16 .b8 param0[16];
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; CHECK-NEXT: st.param.v2.b64 [param0+0], {%[[REG0]], %[[REG1]]}
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; CHECK: .param .align 16 .b8 param1[16];
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; CHECK-NEXT: st.param.v2.b64 [param1+0], {%[[REG2]], %[[REG3]]}
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; CHECK: } // callseq [[CALLSEQ_ID]]
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call void @callee(i128 %0, i128 %1, i128* %2)
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ret void
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}
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; CHECK-LABEL: .visible .func caller_func(
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; CHECK-NEXT: .param .align 16 .b8 caller_func_param_0[16],
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; CHECK-NEXT: .param .align 16 .b8 caller_func_param_1[16],
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define void @caller_func(i128, i128, i128*) {
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start:
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; CHECK-DAG: ld.param.v2.u64 {%[[REG0:rd[0-9]+]], %[[REG1:rd[0-9]+]]}, [caller_func_param_0]
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; CHECK-DAG: ld.param.v2.u64 {%[[REG2:rd[0-9]+]], %[[REG3:rd[0-9]+]]}, [caller_func_param_1]
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; CHECK: { // callseq [[CALLSEQ_ID:[0-9]]], 0
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; CHECK: .param .align 16 .b8 param0[16];
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; CHECK: st.param.v2.b64 [param0+0], {%[[REG0]], %[[REG1]]}
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; CHECK: .param .align 16 .b8 param1[16];
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; CHECK: st.param.v2.b64 [param1+0], {%[[REG2]], %[[REG3]]}
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; CHECK: } // callseq [[CALLSEQ_ID]]
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call void @callee(i128 %0, i128 %1, i128* %2)
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ret void
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}
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