2534dc120a
This patch turns on support for CR bit accesses for Power8 and above. The reason why CR bits are turned on as the default for Power8 and above is that because later architectures make use of builtins and instructions that require CR bit accesses (such as the use of setbc in the vector string isolate predicate and bcd builtins on Power10). This patch also adds the clang portion to allow for turning on CR bits in the front end if the user so desires to. Differential Revision: https://reviews.llvm.org/D124060
61 lines
2.0 KiB
LLVM
61 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 < %s | FileCheck %s
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target datalayout = "e-m:e-i64:64-n32:64"
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target triple = "powerpc64le-unknown-linux-gnu"
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define void @bn_mul_comba8(i64* nocapture %r, i64* nocapture readonly %a, i64* nocapture readonly %b) {
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; CHECK-LABEL: bn_mul_comba8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: std 4, -8(1) # 8-byte Folded Spill
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; CHECK-NEXT: mr 4, 3
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; CHECK-NEXT: ld 3, -8(1) # 8-byte Folded Reload
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; CHECK-NEXT: ld 9, 0(3)
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; CHECK-NEXT: ld 8, 0(5)
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; CHECK-NEXT: mulhdu 7, 8, 9
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; CHECK-NEXT: ld 3, 8(3)
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; CHECK-NEXT: mulld 6, 3, 9
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; CHECK-NEXT: mulhdu 3, 3, 9
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; CHECK-NEXT: addc 6, 6, 7
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; CHECK-NEXT: addze 3, 3
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; CHECK-NEXT: ld 5, 8(5)
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; CHECK-NEXT: mulld 7, 5, 8
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; CHECK-NEXT: mulhdu 5, 5, 8
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; CHECK-NEXT: addc 6, 6, 7
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; CHECK-NEXT: addze 5, 5
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; CHECK-NEXT: add 3, 5, 3
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; CHECK-NEXT: cmpld 3, 5
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; CHECK-NEXT: crmove 20, 0
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; CHECK-NEXT: li 5, 0
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: isel 3, 3, 5, 20
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; CHECK-NEXT: std 3, 0(4)
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; CHECK-NEXT: blr
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%1 = load i64, i64* %a, align 8
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%conv = zext i64 %1 to i128
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%2 = load i64, i64* %b, align 8
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%conv2 = zext i64 %2 to i128
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%mul = mul nuw i128 %conv2, %conv
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%shr = lshr i128 %mul, 64
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%agep = getelementptr inbounds i64, i64* %a, i64 1
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%3 = load i64, i64* %agep, align 8
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%conv14 = zext i64 %3 to i128
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%mul15 = mul nuw i128 %conv14, %conv
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%add17 = add i128 %mul15, %shr
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%shr19 = lshr i128 %add17, 64
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%conv20 = trunc i128 %shr19 to i64
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%bgep = getelementptr inbounds i64, i64* %b, i64 1
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%4 = load i64, i64* %bgep, align 8
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%conv28 = zext i64 %4 to i128
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%mul31 = mul nuw i128 %conv28, %conv2
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%conv32 = and i128 %add17, 18446744073709551615
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%add33 = add i128 %conv32, %mul31
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%shr35 = lshr i128 %add33, 64
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%conv36 = trunc i128 %shr35 to i64
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%add37 = add i64 %conv36, %conv20
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%cmp38 = icmp ult i64 %add37, %conv36
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%conv148 = zext i1 %cmp38 to i64
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store i64 %conv148, i64* %r, align 8
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ret void
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}
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