af430944b3
This patch updates two patterns involving `scalar_to_vector` and `SCALAR_TO_VECTOR_PERMUTED` nodes to be safe for both 64-bit and 32-bit by pulling the patterns out of the 64-bit specific guard. These patterns are matched on POWER8 and above. Differential Revision: https://reviews.llvm.org/D125389
84 lines
2.9 KiB
LLVM
84 lines
2.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr \
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; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64-ibm-aix-xcoff < %s | \
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; RUN: FileCheck %s --check-prefix=AIX-P8-64
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; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr \
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; RUN: -ppc-asm-full-reg-names -mtriple=powerpc-ibm-aix-xcoff < %s | \
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; RUN: FileCheck %s --check-prefix=AIX-P8-32
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; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr \
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; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64-ibm-aix-xcoff < %s | \
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; RUN: FileCheck %s --check-prefix=AIX-P9-64
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; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr \
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; RUN: -ppc-asm-full-reg-names -mtriple=powerpc-ibm-aix-xcoff < %s | \
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; RUN: FileCheck %s --check-prefix=AIX-P9-32
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%d8 = type <8 x double>
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%f1 = type <1 x float>
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%f2 = type <2 x float>
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%f4 = type <4 x float>
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%f8 = type <8 x float>
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%i4 = type <4 x i32>
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define void @test_f2(%f2* %P, %f2* %Q, %f2* %S) {
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; AIX-P8-64-LABEL: test_f2:
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; AIX-P8-64: # %bb.0:
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; AIX-P8-64-NEXT: lfdx f0, 0, r3
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; AIX-P8-64-NEXT: lfdx f1, 0, r4
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; AIX-P8-64-NEXT: xvaddsp vs0, vs0, vs1
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; AIX-P8-64-NEXT: stfdx f0, 0, r5
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; AIX-P8-64-NEXT: blr
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;
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; AIX-P8-32-LABEL: test_f2:
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; AIX-P8-32: # %bb.0:
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; AIX-P8-32-NEXT: lwz r6, L..C0(r2) # %const.0
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; AIX-P8-32-NEXT: li r7, 4
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; AIX-P8-32-NEXT: lxsiwzx v3, 0, r3
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; AIX-P8-32-NEXT: lxsiwzx v0, 0, r4
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; AIX-P8-32-NEXT: lxsiwzx v2, r3, r7
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; AIX-P8-32-NEXT: lxsiwzx v5, r4, r7
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; AIX-P8-32-NEXT: lxvw4x v4, 0, r6
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; AIX-P8-32-NEXT: vperm v2, v3, v2, v4
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; AIX-P8-32-NEXT: vperm v3, v0, v5, v4
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; AIX-P8-32-NEXT: xvaddsp vs0, v2, v3
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; AIX-P8-32-NEXT: xxsldwi vs1, vs0, vs0, 1
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; AIX-P8-32-NEXT: xscvspdpn f0, vs0
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; AIX-P8-32-NEXT: xscvspdpn f1, vs1
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; AIX-P8-32-NEXT: stfs f0, 0(r5)
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; AIX-P8-32-NEXT: stfs f1, 4(r5)
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; AIX-P8-32-NEXT: blr
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;
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; AIX-P9-64-LABEL: test_f2:
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; AIX-P9-64: # %bb.0:
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; AIX-P9-64-NEXT: lfd f0, 0(r3)
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; AIX-P9-64-NEXT: lfd f1, 0(r4)
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; AIX-P9-64-NEXT: xvaddsp vs0, vs0, vs1
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; AIX-P9-64-NEXT: stfd f0, 0(r5)
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; AIX-P9-64-NEXT: blr
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;
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; AIX-P9-32-LABEL: test_f2:
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; AIX-P9-32: # %bb.0:
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; AIX-P9-32-NEXT: lfiwzx f0, 0, r3
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; AIX-P9-32-NEXT: lwz r3, 4(r3)
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; AIX-P9-32-NEXT: xxsldwi vs0, f0, f0, 1
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; AIX-P9-32-NEXT: mtfprwz f1, r3
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; AIX-P9-32-NEXT: lwz r3, 4(r4)
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; AIX-P9-32-NEXT: xxinsertw vs0, vs1, 4
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; AIX-P9-32-NEXT: lfiwzx f1, 0, r4
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; AIX-P9-32-NEXT: mtfprwz f2, r3
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; AIX-P9-32-NEXT: xxsldwi vs1, f1, f1, 1
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; AIX-P9-32-NEXT: xxinsertw vs1, vs2, 4
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; AIX-P9-32-NEXT: xvaddsp vs0, vs0, vs1
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; AIX-P9-32-NEXT: xscvspdpn f1, vs0
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; AIX-P9-32-NEXT: xxsldwi vs0, vs0, vs0, 1
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; AIX-P9-32-NEXT: xscvspdpn f0, vs0
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; AIX-P9-32-NEXT: stfs f1, 0(r5)
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; AIX-P9-32-NEXT: stfs f0, 4(r5)
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; AIX-P9-32-NEXT: blr
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%p = load %f2, %f2* %P
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%q = load %f2, %f2* %Q
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%R = fadd %f2 %p, %q
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store %f2 %R, %f2* %S
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ret void
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}
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