af430944b3
This patch updates two patterns involving `scalar_to_vector` and `SCALAR_TO_VECTOR_PERMUTED` nodes to be safe for both 64-bit and 32-bit by pulling the patterns out of the 64-bit specific guard. These patterns are matched on POWER8 and above. Differential Revision: https://reviews.llvm.org/D125389
41 lines
1.8 KiB
LLVM
41 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names | FileCheck --check-prefix=CHECK-LE \
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; RUN: -implicit-check-not vmrg -implicit-check-not=vperm %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu < %s \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names | FileCheck \
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; RUN: -implicit-check-not vmrg -implicit-check-not=vperm %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-ibm-aix-xcoff < %s \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names | FileCheck \
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; RUN: -implicit-check-not vmrg -implicit-check-not=vperm %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc-ibm-aix-xcoff < %s \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names | FileCheck \
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; RUN: --check-prefix=CHECK-AIX-32 -implicit-check-not vmrg \
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; RUN: -implicit-check-not=vperm %s
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define <16 x i8> @test(i32* %s, i32* %t) {
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; CHECK-LE-LABEL: test:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: lfiwzx f0, 0, r3
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; CHECK-LE-NEXT: xxspltw v2, vs0, 1
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; CHECK-LE-NEXT: blr
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;
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; CHECK-LABEL: test:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lfiwzx f0, 0, r3
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; CHECK-NEXT: xxspltw v2, vs0, 1
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; CHECK-NEXT: blr
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;
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; CHECK-AIX-32-LABEL: test:
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; CHECK-AIX-32: # %bb.0: # %entry
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; CHECK-AIX-32-NEXT: lfiwzx f0, 0, r3
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; CHECK-AIX-32-NEXT: xxspltw v2, vs0, 1
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; CHECK-AIX-32-NEXT: blr
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entry:
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%0 = bitcast i32* %s to <4 x i8>*
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%1 = load <4 x i8>, <4 x i8>* %0, align 4
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%2 = shufflevector <4 x i8> %1, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
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ret <16 x i8> %2
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}
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