4bcfc41846
This matches what we do in IR. For the RISC-V test case, this allows us to use -8 for the AND mask instead of materializing a constant in a register. Reviewed By: spatel Differential Revision: https://reviews.llvm.org/D127335
40 lines
1.2 KiB
LLVM
40 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s | FileCheck %s
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; This test has multiple opportunities for SimplifyDemandedBits after type
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; legalization. There are 2 opportunities on the chain feeding the LHS of the
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; shl. And one opportunity on the shift amount. We previously weren't managing
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; the DAGCombiner worklist correctly and failed to get the RHS.
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define i32 @foo(i32 %x, i32 %y, i32 %z) {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mulw a0, a0, a0
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; CHECK-NEXT: addiw a0, a0, 1
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; CHECK-NEXT: mulw a0, a0, a0
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; CHECK-NEXT: addw a0, a0, a2
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; CHECK-NEXT: addiw a0, a0, 1
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; CHECK-NEXT: sllw a0, a0, a1
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; CHECK-NEXT: ret
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%b = mul i32 %x, %x
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%c = add i32 %b, 1
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%d = mul i32 %c, %c
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%e = add i32 %d, %z
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%f = add i32 %e, 1
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%g = shl i32 %f, %y
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ret i32 %g
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}
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; The sign bit of an nsw self multiply is 0. Make sure we can use this to
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; convert the AND constant to -8.
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define i64 @mul_self_nsw_sign(i64 %x) {
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; CHECK-LABEL: mul_self_nsw_sign:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mul a0, a0, a0
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; CHECK-NEXT: andi a0, a0, -8
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; CHECK-NEXT: ret
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%a = mul nsw i64 %x, %x
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%b = and i64 %a, 9223372036854775800
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ret i64 %b
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}
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