08c9fb8447
This patch fixes another bug in the RVV frame lowering. While some frame objects with non-default stack IDs (such scalable-vector alloca instructions) are considered in the target-independent max alignment calculations, others (for example, during calling-convention lowering) are not. This means we'd occasionally align the base of the stack to only 16 bytes, with no way to ensure that the RVV section contained within that is aligned to anything higher. Reviewed By: StephenFan Differential Revision: https://reviews.llvm.org/D125973
85 lines
3.2 KiB
LLVM
85 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+m,+v < %s | FileCheck %s --check-prefixes=CHECK,RV32
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; RUN: llc -mtriple=riscv64 -mattr=+m,+v < %s | FileCheck %s --check-prefixes=CHECK,RV64
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; Check that we correctly scale the split part indirect offsets by VSCALE.
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define <vscale x 32 x i32> @callee_scalable_vector_split_indirect(<vscale x 32 x i32> %x, <vscale x 32 x i32> %y) {
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; CHECK-LABEL: callee_scalable_vector_split_indirect:
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; CHECK: # %bb.0:
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: slli a1, a1, 3
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; CHECK-NEXT: add a1, a0, a1
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; CHECK-NEXT: vl8re32.v v24, (a0)
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; CHECK-NEXT: vl8re32.v v0, (a1)
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; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
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; CHECK-NEXT: vadd.vv v8, v8, v24
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; CHECK-NEXT: vadd.vv v16, v16, v0
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; CHECK-NEXT: ret
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%a = add <vscale x 32 x i32> %x, %y
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ret <vscale x 32 x i32> %a
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}
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; Call the function above. Check that we set the arguments correctly.
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define <vscale x 32 x i32> @caller_scalable_vector_split_indirect(<vscale x 32 x i32> %x) {
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; RV32-LABEL: caller_scalable_vector_split_indirect:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -144
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; RV32-NEXT: .cfi_def_cfa_offset 144
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; RV32-NEXT: sw ra, 140(sp) # 4-byte Folded Spill
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; RV32-NEXT: .cfi_offset ra, -4
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; RV32-NEXT: addi s0, sp, 144
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; RV32-NEXT: .cfi_def_cfa s0, 0
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; RV32-NEXT: csrr a0, vlenb
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; RV32-NEXT: slli a0, a0, 4
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; RV32-NEXT: sub sp, sp, a0
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; RV32-NEXT: andi sp, sp, -128
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; RV32-NEXT: csrr a0, vlenb
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; RV32-NEXT: slli a0, a0, 3
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; RV32-NEXT: addi a1, sp, 128
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; RV32-NEXT: add a0, a1, a0
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; RV32-NEXT: vs8r.v v16, (a0)
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; RV32-NEXT: addi a0, sp, 128
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; RV32-NEXT: vs8r.v v8, (a0)
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; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, mu
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; RV32-NEXT: vmv.v.i v8, 0
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; RV32-NEXT: addi a0, sp, 128
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; RV32-NEXT: vmv.v.i v16, 0
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; RV32-NEXT: call callee_scalable_vector_split_indirect@plt
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; RV32-NEXT: addi sp, s0, -144
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; RV32-NEXT: lw ra, 140(sp) # 4-byte Folded Reload
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; RV32-NEXT: addi sp, sp, 144
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; RV32-NEXT: ret
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;
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; RV64-LABEL: caller_scalable_vector_split_indirect:
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; RV64: # %bb.0:
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; RV64-NEXT: addi sp, sp, -144
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; RV64-NEXT: .cfi_def_cfa_offset 144
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; RV64-NEXT: sd ra, 136(sp) # 8-byte Folded Spill
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; RV64-NEXT: .cfi_offset ra, -8
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; RV64-NEXT: addi s0, sp, 144
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; RV64-NEXT: .cfi_def_cfa s0, 0
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; RV64-NEXT: csrr a0, vlenb
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; RV64-NEXT: slli a0, a0, 4
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; RV64-NEXT: sub sp, sp, a0
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; RV64-NEXT: andi sp, sp, -128
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; RV64-NEXT: csrr a0, vlenb
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; RV64-NEXT: slli a0, a0, 3
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; RV64-NEXT: addi a1, sp, 128
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; RV64-NEXT: add a0, a1, a0
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; RV64-NEXT: vs8r.v v16, (a0)
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; RV64-NEXT: addi a0, sp, 128
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; RV64-NEXT: vs8r.v v8, (a0)
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; RV64-NEXT: vsetvli a0, zero, e32, m8, ta, mu
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; RV64-NEXT: vmv.v.i v8, 0
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; RV64-NEXT: addi a0, sp, 128
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; RV64-NEXT: vmv.v.i v16, 0
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; RV64-NEXT: call callee_scalable_vector_split_indirect@plt
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; RV64-NEXT: addi sp, s0, -144
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; RV64-NEXT: ld ra, 136(sp) # 8-byte Folded Reload
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; RV64-NEXT: addi sp, sp, 144
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; RV64-NEXT: ret
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%c = alloca i64
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%a = call <vscale x 32 x i32> @callee_scalable_vector_split_indirect(<vscale x 32 x i32> zeroinitializer, <vscale x 32 x i32> %x)
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ret <vscale x 32 x i32> %a
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}
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