1ecc3d86ae
Pulled out of D77804 as its going to be easier to address the regressions individually. This patch allows SimplifyDemandedBits to call SimplifyMultipleUseDemandedBits in cases where the source operand has other uses, enabling us to peek through the shifted value if we don't demand all the bits/elts. The lost RISCV gorc2 fold shouldn't be a problem - instcombine would have already destroyed that pattern - see https://github.com/llvm/llvm-project/issues/50553 Differential Revision: https://reviews.llvm.org/D124839
87 lines
2.7 KiB
LLVM
87 lines
2.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefix=RV32
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; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefix=RV64
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; This test would lead one of the DAGCombiner's visitVSELECT optimizations to
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; call getSetCCResultType, from which we'd return an invalid MVT (<3 x i1>)
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; upon seeing that the V extension is enabled. The invalid MVT has a null
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; Type*, which then segfaulted when accessed (as an EVT).
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define void @vec3_setcc_crash(<3 x i8>* %in, <3 x i8>* %out) {
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; RV32-LABEL: vec3_setcc_crash:
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; RV32: # %bb.0:
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; RV32-NEXT: lw a0, 0(a0)
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; RV32-NEXT: slli a2, a0, 8
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; RV32-NEXT: slli a3, a0, 24
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; RV32-NEXT: slli a4, a0, 16
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; RV32-NEXT: srai a5, a4, 24
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; RV32-NEXT: srai a3, a3, 24
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; RV32-NEXT: bgtz a5, .LBB0_2
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; RV32-NEXT: # %bb.1:
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; RV32-NEXT: li a5, 0
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; RV32-NEXT: j .LBB0_3
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; RV32-NEXT: .LBB0_2:
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; RV32-NEXT: srli a5, a4, 24
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; RV32-NEXT: .LBB0_3:
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; RV32-NEXT: srai a4, a2, 24
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; RV32-NEXT: slli a2, a5, 8
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; RV32-NEXT: mv a5, a0
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; RV32-NEXT: bgtz a3, .LBB0_5
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; RV32-NEXT: # %bb.4:
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; RV32-NEXT: li a5, 0
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; RV32-NEXT: .LBB0_5:
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; RV32-NEXT: andi a3, a5, 255
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; RV32-NEXT: or a2, a3, a2
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; RV32-NEXT: bgtz a4, .LBB0_7
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; RV32-NEXT: # %bb.6:
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; RV32-NEXT: li a0, 0
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; RV32-NEXT: j .LBB0_8
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; RV32-NEXT: .LBB0_7:
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; RV32-NEXT: srli a0, a0, 16
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; RV32-NEXT: .LBB0_8:
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; RV32-NEXT: sb a0, 2(a1)
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; RV32-NEXT: sh a2, 0(a1)
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; RV32-NEXT: ret
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;
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; RV64-LABEL: vec3_setcc_crash:
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; RV64: # %bb.0:
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; RV64-NEXT: lwu a0, 0(a0)
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; RV64-NEXT: slli a2, a0, 40
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; RV64-NEXT: slli a3, a0, 56
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; RV64-NEXT: slli a4, a0, 48
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; RV64-NEXT: srai a5, a4, 56
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; RV64-NEXT: srai a3, a3, 56
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; RV64-NEXT: bgtz a5, .LBB0_2
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; RV64-NEXT: # %bb.1:
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; RV64-NEXT: li a5, 0
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; RV64-NEXT: j .LBB0_3
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; RV64-NEXT: .LBB0_2:
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; RV64-NEXT: srli a5, a4, 56
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; RV64-NEXT: .LBB0_3:
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; RV64-NEXT: srai a4, a2, 56
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; RV64-NEXT: slli a2, a5, 8
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; RV64-NEXT: mv a5, a0
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; RV64-NEXT: bgtz a3, .LBB0_5
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; RV64-NEXT: # %bb.4:
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; RV64-NEXT: li a5, 0
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; RV64-NEXT: .LBB0_5:
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; RV64-NEXT: andi a3, a5, 255
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; RV64-NEXT: or a2, a3, a2
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; RV64-NEXT: bgtz a4, .LBB0_7
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; RV64-NEXT: # %bb.6:
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; RV64-NEXT: li a0, 0
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; RV64-NEXT: j .LBB0_8
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; RV64-NEXT: .LBB0_7:
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; RV64-NEXT: srli a0, a0, 16
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; RV64-NEXT: .LBB0_8:
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; RV64-NEXT: sb a0, 2(a1)
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; RV64-NEXT: sh a2, 0(a1)
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; RV64-NEXT: ret
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%a = load <3 x i8>, <3 x i8>* %in
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%cmp = icmp sgt <3 x i8> %a, zeroinitializer
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%c = select <3 x i1> %cmp, <3 x i8> %a, <3 x i8> zeroinitializer
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store <3 x i8> %c, <3 x i8>* %out
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ret void
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}
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