eaa78035c6
* Set MaxStoresPerMemcpy and MaxStoresPerMemset to 2. * Optimize stores of replicated values in SystemZ::combineSTORE(). This handles the now expanded memory operations and as well some other pre-existing cases. * Reject a big displacement in isLegalAddressingMode() for a vector type. * Return true from shouldConsiderGEPOffsetSplit(). Reviewed By: Ulrich Weigand Differential Revision: https://reviews.llvm.org/D122105
30 lines
1018 B
LLVM
30 lines
1018 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s
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;
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; Test that DAGCombiner does not change the addressing as the displacements
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; are known to be out of range. Only one addition is needed.
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define void @fun(<2 x i64>* %Src, <2 x i64>* %Dst) {
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; CHECK-LABEL: fun:
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; CHECK: # %bb.0:
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; CHECK-NEXT: aghi %r2, 4096
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; CHECK-NEXT: vl %v0, 0(%r2), 3
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; CHECK-NEXT: vst %v0, 0(%r3), 3
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; CHECK-NEXT: vl %v0, 16(%r2), 3
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; CHECK-NEXT: vst %v0, 0(%r3), 3
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; CHECK-NEXT: br %r14
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%1 = bitcast <2 x i64>* %Src to i8*
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%splitgep = getelementptr i8, i8* %1, i64 4096
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%2 = bitcast i8* %splitgep to <2 x i64>*
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%V0 = load <2 x i64>, <2 x i64>* %2, align 8
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store volatile <2 x i64> %V0, <2 x i64>* %Dst, align 8
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%3 = getelementptr i8, i8* %splitgep, i64 16
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%4 = bitcast i8* %3 to <2 x i64>*
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%V1 = load <2 x i64>, <2 x i64>* %4, align 8
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store volatile <2 x i64> %V1, <2 x i64>* %Dst, align 8
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ret void
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}
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