05c3fe075d
FastISel tries to fold loads into the single using instruction. However, if the register has fixups, then there may be additional uses through an alias of the register. In particular, this fixes the problem reported at https://reviews.llvm.org/D119432#3507087. The load register is (at the time of load folding) only used in a single call instruction. However, selection of the bitcast has added a fixup between the load register and the cross-BB register of the bitcast result. After fixups are applied, there would now be two uses of the load register, so load folding is not legal. Differential Revision: https://reviews.llvm.org/D125459
37 lines
1.1 KiB
LLVM
37 lines
1.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 -mtriple=x86_64-- -verify-machineinstrs < %s | FileCheck %s
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define void @repro(i8** %a0, i1 %a1) nounwind {
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; CHECK-LABEL: repro:
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; CHECK: # %bb.0:
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; CHECK-NEXT: subq $24, %rsp
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; CHECK-NEXT: movb %sil, %al
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; CHECK-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
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; CHECK-NEXT: callq *%rax
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; CHECK-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload
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; CHECK-NEXT: testb $1, %al
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; CHECK-NEXT: jne .LBB0_1
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; CHECK-NEXT: jmp .LBB0_2
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; CHECK-NEXT: .LBB0_1: # %bb1
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; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
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; CHECK-NEXT: callq *%rax
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; CHECK-NEXT: addq $24, %rsp
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; CHECK-NEXT: retq
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; CHECK-NEXT: .LBB0_2: # %bb2
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; CHECK-NEXT: addq $24, %rsp
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; CHECK-NEXT: retq
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%tmp0 = load i8*, i8** %a0
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%tmp1 = bitcast i8* %tmp0 to void ()*
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call void %tmp1()
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br i1 %a1, label %bb1, label %bb2
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bb1:
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call void %tmp1()
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ret void
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bb2:
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ret void
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}
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