3075e5d2ef
Don't try to directly use the with.overflow flag result in a cmov if we need to materialize constants between the instruction producing the overflow flag and the cmov. The current code is careful to check that there are no other instructions in between, but misses the constant materialization case (which may clobber eflags via xor or constant expression evaluation). Fixes https://github.com/llvm/llvm-project/issues/54369. Differential Revision: https://reviews.llvm.org/D122825
41 lines
1.3 KiB
LLVM
41 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-- -O0 < %s | FileCheck %s
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define i64 @adder(i64 %lhs, i64 %rhs) {
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; CHECK-LABEL: adder:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addq %rsi, %rdi
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; CHECK-NEXT: seto %dl
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: # kill: def $rax killed $eax
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; CHECK-NEXT: movl $148, %ecx
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; CHECK-NEXT: testb $1, %dl
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; CHECK-NEXT: cmovneq %rcx, %rax
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; CHECK-NEXT: retq
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%res = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %lhs, i64 %rhs)
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%errorbit = extractvalue { i64, i1 } %res, 1
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%errorval = select i1 %errorbit, i64 148, i64 0
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ret i64 %errorval
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}
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@a = global i32 0, align 4
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define i64 @adder_constexpr(i64 %lhs, i64 %rhs) {
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; CHECK-LABEL: adder_constexpr:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addq %rsi, %rdi
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; CHECK-NEXT: seto %dl
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; CHECK-NEXT: movq a@GOTPCREL(%rip), %rax
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; CHECK-NEXT: addq $5, %rax
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; CHECK-NEXT: movl $148, %ecx
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; CHECK-NEXT: testb $1, %dl
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; CHECK-NEXT: cmovneq %rcx, %rax
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; CHECK-NEXT: retq
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%res = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %lhs, i64 %rhs)
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%errorbit = extractvalue { i64, i1 } %res, 1
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%errorval = select i1 %errorbit, i64 148, i64 add (i64 ptrtoint (i32* @a to i64), i64 5)
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ret i64 %errorval
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}
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declare { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %a, i64 %b)
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