c0e06c7448
The and/or of icmps fold is also applied in reassociated form. However, this currently only happens for bitwise and of bitwise and, but not for bitwise and of logical and (or other combinations, but this is the one being addressed here). We can do this for bitwise+logical combinations as well, but need to be a bit careful about which of the resulting ands are logical: https://alive2.llvm.org/ce/z/WYSjGh https://alive2.llvm.org/ce/z/guxYnz https://alive2.llvm.org/ce/z/S5SYxY https://alive2.llvm.org/ce/z/2rAWeW
289 lines
8.4 KiB
LLVM
289 lines
8.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=instcombine -S | FileCheck %s
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define i1 @test2(i1 %X, i1 %Y) {
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; CHECK-LABEL: @test2(
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; CHECK-NEXT: [[A:%.*]] = and i1 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret i1 [[A]]
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;
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%a = and i1 %X, %Y
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%b = and i1 %a, %X
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ret i1 %b
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}
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define i1 @test2_logical(i1 %X, i1 %Y) {
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; CHECK-LABEL: @test2_logical(
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; CHECK-NEXT: [[A:%.*]] = select i1 [[X:%.*]], i1 [[Y:%.*]], i1 false
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; CHECK-NEXT: ret i1 [[A]]
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;
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%a = select i1 %X, i1 %Y, i1 false
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%b = select i1 %a, i1 %X, i1 false
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ret i1 %b
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}
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define i32 @test3(i32 %X, i32 %Y) {
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; CHECK-LABEL: @test3(
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; CHECK-NEXT: [[A:%.*]] = and i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret i32 [[A]]
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;
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%a = and i32 %X, %Y
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%b = and i32 %Y, %a
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ret i32 %b
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}
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define i1 @test7(i32 %i, i1 %b) {
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; CHECK-LABEL: @test7(
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[I:%.*]], 0
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; CHECK-NEXT: [[TMP2:%.*]] = and i1 [[TMP1]], [[B:%.*]]
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; CHECK-NEXT: ret i1 [[TMP2]]
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;
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%cmp1 = icmp slt i32 %i, 1
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%cmp2 = icmp sgt i32 %i, -1
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%and1 = and i1 %cmp1, %b
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%and2 = and i1 %and1, %cmp2
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ret i1 %and2
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}
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define i1 @test7_logical(i32 %i, i1 %b) {
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; CHECK-LABEL: @test7_logical(
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[I:%.*]], 0
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; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i1 [[B:%.*]], i1 false
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; CHECK-NEXT: ret i1 [[TMP2]]
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;
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%cmp1 = icmp slt i32 %i, 1
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%cmp2 = icmp sgt i32 %i, -1
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%and1 = select i1 %cmp1, i1 %b, i1 false
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%and2 = select i1 %and1, i1 %cmp2, i1 false
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ret i1 %and2
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}
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define i1 @test8(i32 %i) {
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; CHECK-LABEL: @test8(
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; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[I:%.*]], -1
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 13
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; CHECK-NEXT: ret i1 [[TMP2]]
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;
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%cmp1 = icmp ne i32 %i, 0
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%cmp2 = icmp ult i32 %i, 14
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%cond = and i1 %cmp1, %cmp2
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ret i1 %cond
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}
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define i1 @test8_logical(i32 %i) {
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; CHECK-LABEL: @test8_logical(
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; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[I:%.*]], -1
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 13
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; CHECK-NEXT: ret i1 [[TMP2]]
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;
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%cmp1 = icmp ne i32 %i, 0
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%cmp2 = icmp ult i32 %i, 14
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%cond = select i1 %cmp1, i1 %cmp2, i1 false
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ret i1 %cond
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}
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define <2 x i1> @test8vec(<2 x i32> %i) {
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; CHECK-LABEL: @test8vec(
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; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[I:%.*]], <i32 -1, i32 -1>
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ult <2 x i32> [[TMP1]], <i32 13, i32 13>
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; CHECK-NEXT: ret <2 x i1> [[TMP2]]
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;
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%cmp1 = icmp ne <2 x i32> %i, zeroinitializer
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%cmp2 = icmp ult <2 x i32> %i, <i32 14, i32 14>
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%cond = and <2 x i1> %cmp1, %cmp2
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ret <2 x i1> %cond
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}
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; combine -x & 1 into x & 1
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define i64 @test9(i64 %x) {
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; CHECK-LABEL: @test9(
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; CHECK-NEXT: [[AND:%.*]] = and i64 [[X:%.*]], 1
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; CHECK-NEXT: ret i64 [[AND]]
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;
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%sub = sub nsw i64 0, %x
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%and = and i64 %sub, 1
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ret i64 %and
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}
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; combine -x & 1 into x & 1
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define <2 x i64> @test9vec(<2 x i64> %x) {
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; CHECK-LABEL: @test9vec(
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; CHECK-NEXT: [[AND:%.*]] = and <2 x i64> [[X:%.*]], <i64 1, i64 1>
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; CHECK-NEXT: ret <2 x i64> [[AND]]
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;
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%sub = sub nsw <2 x i64> <i64 0, i64 0>, %x
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%and = and <2 x i64> %sub, <i64 1, i64 1>
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ret <2 x i64> %and
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}
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define i64 @test10(i64 %x) {
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; CHECK-LABEL: @test10(
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; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[X:%.*]], -2
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; CHECK-NEXT: [[ADD:%.*]] = sub i64 0, [[TMP1]]
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; CHECK-NEXT: ret i64 [[ADD]]
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;
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%sub = sub nsw i64 0, %x
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%and = and i64 %sub, 1
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%add = add i64 %sub, %and
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ret i64 %add
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}
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; (1 << x) & 1 --> zext(x == 0)
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define i8 @and1_shl1_is_cmp_eq_0(i8 %x) {
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; CHECK-LABEL: @and1_shl1_is_cmp_eq_0(
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 [[X:%.*]], 0
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; CHECK-NEXT: [[AND:%.*]] = zext i1 [[TMP1]] to i8
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; CHECK-NEXT: ret i8 [[AND]]
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;
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%sh = shl i8 1, %x
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%and = and i8 %sh, 1
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ret i8 %and
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}
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; Don't do it if the shift has another use.
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define i8 @and1_shl1_is_cmp_eq_0_multiuse(i8 %x) {
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; CHECK-LABEL: @and1_shl1_is_cmp_eq_0_multiuse(
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; CHECK-NEXT: [[SH:%.*]] = shl i8 1, [[X:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = and i8 [[SH]], 1
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; CHECK-NEXT: [[ADD:%.*]] = add i8 [[SH]], [[AND]]
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; CHECK-NEXT: ret i8 [[ADD]]
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;
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%sh = shl i8 1, %x
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%and = and i8 %sh, 1
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%add = add i8 %sh, %and
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ret i8 %add
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}
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; (1 << x) & 1 --> zext(x == 0)
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define <2 x i8> @and1_shl1_is_cmp_eq_0_vec(<2 x i8> %x) {
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; CHECK-LABEL: @and1_shl1_is_cmp_eq_0_vec(
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i8> [[X:%.*]], zeroinitializer
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; CHECK-NEXT: [[AND:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i8>
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; CHECK-NEXT: ret <2 x i8> [[AND]]
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;
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%sh = shl <2 x i8> <i8 1, i8 1>, %x
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%and = and <2 x i8> %sh, <i8 1, i8 1>
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ret <2 x i8> %and
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}
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define <2 x i8> @and1_shl1_is_cmp_eq_0_vec_undef(<2 x i8> %x) {
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; CHECK-LABEL: @and1_shl1_is_cmp_eq_0_vec_undef(
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i8> [[X:%.*]], zeroinitializer
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; CHECK-NEXT: [[AND:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i8>
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; CHECK-NEXT: ret <2 x i8> [[AND]]
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;
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%sh = shl <2 x i8> <i8 1, i8 undef>, %x
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%and = and <2 x i8> %sh, <i8 1, i8 undef>
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ret <2 x i8> %and
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}
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; The mask is unnecessary.
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define i8 @and1_lshr1_is_cmp_eq_0(i8 %x) {
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; CHECK-LABEL: @and1_lshr1_is_cmp_eq_0(
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; CHECK-NEXT: [[SH:%.*]] = lshr i8 1, [[X:%.*]]
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; CHECK-NEXT: ret i8 [[SH]]
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;
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%sh = lshr i8 1, %x
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%and = and i8 %sh, 1
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ret i8 %and
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}
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define i8 @and1_lshr1_is_cmp_eq_0_multiuse(i8 %x) {
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; CHECK-LABEL: @and1_lshr1_is_cmp_eq_0_multiuse(
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; CHECK-NEXT: [[SH:%.*]] = lshr i8 1, [[X:%.*]]
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; CHECK-NEXT: [[ADD:%.*]] = shl nuw nsw i8 [[SH]], 1
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; CHECK-NEXT: ret i8 [[ADD]]
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;
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%sh = lshr i8 1, %x
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%and = and i8 %sh, 1
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%add = add i8 %sh, %and
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ret i8 %add
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}
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; The mask is unnecessary.
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define <2 x i8> @and1_lshr1_is_cmp_eq_0_vec(<2 x i8> %x) {
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; CHECK-LABEL: @and1_lshr1_is_cmp_eq_0_vec(
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; CHECK-NEXT: [[SH:%.*]] = lshr <2 x i8> <i8 1, i8 1>, [[X:%.*]]
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; CHECK-NEXT: ret <2 x i8> [[SH]]
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;
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%sh = lshr <2 x i8> <i8 1, i8 1>, %x
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%and = and <2 x i8> %sh, <i8 1, i8 1>
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ret <2 x i8> %and
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}
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define <2 x i8> @and1_lshr1_is_cmp_eq_0_vec_undef(<2 x i8> %x) {
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; CHECK-LABEL: @and1_lshr1_is_cmp_eq_0_vec_undef(
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i8> [[X:%.*]], zeroinitializer
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; CHECK-NEXT: [[AND:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i8>
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; CHECK-NEXT: ret <2 x i8> [[AND]]
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;
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%sh = lshr <2 x i8> <i8 1, i8 undef>, %x
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%and = and <2 x i8> %sh, <i8 1, i8 undef>
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ret <2 x i8> %and
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}
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; The add in this test is unnecessary because the LSBs of the LHS are 0 and the 'and' only consumes bits from those LSBs. It doesn't matter what happens to the upper bits.
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define i32 @test11(i32 %a, i32 %b) {
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; CHECK-LABEL: @test11(
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; CHECK-NEXT: [[X:%.*]] = shl i32 [[A:%.*]], 8
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; CHECK-NEXT: [[Z:%.*]] = and i32 [[B:%.*]], 128
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; CHECK-NEXT: [[W:%.*]] = mul i32 [[Z]], [[X]]
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; CHECK-NEXT: ret i32 [[W]]
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;
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%x = shl i32 %a, 8
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%y = add i32 %x, %b
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%z = and i32 %y, 128
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%w = mul i32 %z, %x ; to keep the shift from being removed
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ret i32 %w
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}
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; The add in this test is unnecessary because the LSBs of the RHS are 0 and the 'and' only consumes bits from those LSBs. It doesn't matter what happens to the upper bits.
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define i32 @test12(i32 %a, i32 %b) {
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; CHECK-LABEL: @test12(
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; CHECK-NEXT: [[X:%.*]] = shl i32 [[A:%.*]], 8
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; CHECK-NEXT: [[Z:%.*]] = and i32 [[B:%.*]], 128
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; CHECK-NEXT: [[W:%.*]] = mul i32 [[Z]], [[X]]
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; CHECK-NEXT: ret i32 [[W]]
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;
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%x = shl i32 %a, 8
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%y = add i32 %b, %x
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%z = and i32 %y, 128
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%w = mul i32 %z, %x ; to keep the shift from being removed
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ret i32 %w
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}
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; The sub in this test is unnecessary because the LSBs of the RHS are 0 and the 'and' only consumes bits from those LSBs. It doesn't matter what happens to the upper bits.
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define i32 @test13(i32 %a, i32 %b) {
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; CHECK-LABEL: @test13(
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; CHECK-NEXT: [[X:%.*]] = shl i32 [[A:%.*]], 8
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; CHECK-NEXT: [[Z:%.*]] = and i32 [[B:%.*]], 128
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; CHECK-NEXT: [[W:%.*]] = mul i32 [[Z]], [[X]]
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; CHECK-NEXT: ret i32 [[W]]
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;
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%x = shl i32 %a, 8
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%y = sub i32 %b, %x
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%z = and i32 %y, 128
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%w = mul i32 %z, %x ; to keep the shift from being removed
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ret i32 %w
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}
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; The sub in this test cannot be removed because we need to keep the negation of %b. TODO: But we should be able to replace the LHS of it with a 0.
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define i32 @test14(i32 %a, i32 %b) {
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; CHECK-LABEL: @test14(
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; CHECK-NEXT: [[X:%.*]] = shl i32 [[A:%.*]], 8
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; CHECK-NEXT: [[Y:%.*]] = sub i32 0, [[B:%.*]]
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; CHECK-NEXT: [[Z:%.*]] = and i32 [[Y]], 128
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; CHECK-NEXT: [[W:%.*]] = mul i32 [[Z]], [[X]]
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; CHECK-NEXT: ret i32 [[W]]
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;
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%x = shl i32 %a, 8
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%y = sub i32 %x, %b
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%z = and i32 %y, 128
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%w = mul i32 %z, %x ; to keep the shift from being removed
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ret i32 %w
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}
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