1881711fbb
This removes memset with undef char. We already do this for stores of undef value. This comes with the caveat that this optimization is not, strictly speaking, legal for undef values, because we might be overwriting a poison value. However, our entire load/store model currently still operates on undef values, so we need to support undef here as well for internal consistency. Once https://github.com/llvm/llvm-project/issues/52930 is resolved, these and related folds can be limited to poison -- I've added FIXMEs to that effect. Differential Revision: https://reviews.llvm.org/D124173
344 lines
9.1 KiB
LLVM
344 lines
9.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=instcombine -S | FileCheck %s
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; FIXME: This is technically incorrect because it might overwrite a poison
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; value. Stop folding it once #52930 is resolved.
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define void @store_of_undef(i32* %P) {
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; CHECK-LABEL: @store_of_undef(
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; CHECK-NEXT: ret void
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;
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store i32 undef, i32* %P
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ret void
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}
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define void @store_of_poison(i32* %P) {
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; CHECK-LABEL: @store_of_poison(
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; CHECK-NEXT: ret void
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;
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store i32 poison, i32* %P
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ret void
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}
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define void @store_into_undef(i32* %P) {
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; CHECK-LABEL: @store_into_undef(
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; CHECK-NEXT: store i32 123, i32* undef, align 4
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; CHECK-NEXT: ret void
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;
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store i32 123, i32* undef
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ret void
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}
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define void @store_into_null(i32* %P) {
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; CHECK-LABEL: @store_into_null(
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; CHECK-NEXT: store i32 poison, i32* null, align 4294967296
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; CHECK-NEXT: ret void
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;
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store i32 124, i32* null
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ret void
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}
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define void @test2(i32* %P) {
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; CHECK-LABEL: @test2(
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; CHECK-NEXT: ret void
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;
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%X = load i32, i32* %P
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%Y = add i32 %X, 0
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store i32 %Y, i32* %P
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ret void
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}
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define void @store_at_gep_off_null_inbounds(i64 %offset) {
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; CHECK-LABEL: @store_at_gep_off_null_inbounds(
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; CHECK-NEXT: [[PTR:%.*]] = getelementptr inbounds i32, i32* null, i64 [[OFFSET:%.*]]
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; CHECK-NEXT: store i32 poison, i32* [[PTR]], align 4
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; CHECK-NEXT: ret void
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;
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%ptr = getelementptr inbounds i32, i32 *null, i64 %offset
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store i32 24, i32* %ptr
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ret void
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}
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define void @store_at_gep_off_null_not_inbounds(i64 %offset) {
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; CHECK-LABEL: @store_at_gep_off_null_not_inbounds(
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; CHECK-NEXT: [[PTR:%.*]] = getelementptr i32, i32* null, i64 [[OFFSET:%.*]]
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; CHECK-NEXT: store i32 poison, i32* [[PTR]], align 4
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; CHECK-NEXT: ret void
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;
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%ptr = getelementptr i32, i32 *null, i64 %offset
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store i32 24, i32* %ptr
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ret void
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}
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define void @store_at_gep_off_no_null_opt(i64 %offset) #0 {
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; CHECK-LABEL: @store_at_gep_off_no_null_opt(
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; CHECK-NEXT: [[PTR:%.*]] = getelementptr inbounds i32, i32* null, i64 [[OFFSET:%.*]]
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; CHECK-NEXT: store i32 24, i32* [[PTR]], align 4
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; CHECK-NEXT: ret void
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;
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%ptr = getelementptr inbounds i32, i32 *null, i64 %offset
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store i32 24, i32* %ptr
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ret void
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}
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attributes #0 = { null_pointer_is_valid }
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;; Simple sinking tests
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; "if then else"
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define i32 @test3(i1 %C) {
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; CHECK-LABEL: @test3(
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; CHECK-NEXT: br i1 [[C:%.*]], label [[COND:%.*]], label [[COND2:%.*]]
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; CHECK: Cond:
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; CHECK-NEXT: br label [[CONT:%.*]]
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; CHECK: Cond2:
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; CHECK-NEXT: br label [[CONT]]
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; CHECK: Cont:
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; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i32 [ 47, [[COND2]] ], [ -987654321, [[COND]] ]
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; CHECK-NEXT: ret i32 [[STOREMERGE]]
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;
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%A = alloca i32
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br i1 %C, label %Cond, label %Cond2
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Cond:
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store i32 -987654321, i32* %A
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br label %Cont
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Cond2:
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store i32 47, i32* %A
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br label %Cont
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Cont:
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%V = load i32, i32* %A
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ret i32 %V
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}
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; "if then"
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define i32 @test4(i1 %C) {
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; CHECK-LABEL: @test4(
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; CHECK-NEXT: br i1 [[C:%.*]], label [[COND:%.*]], label [[CONT:%.*]]
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; CHECK: Cond:
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; CHECK-NEXT: br label [[CONT]]
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; CHECK: Cont:
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; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i32 [ -987654321, [[COND]] ], [ 47, [[TMP0:%.*]] ]
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; CHECK-NEXT: ret i32 [[STOREMERGE]]
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;
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%A = alloca i32
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store i32 47, i32* %A
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br i1 %C, label %Cond, label %Cont
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Cond:
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store i32 -987654321, i32* %A
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br label %Cont
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Cont:
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%V = load i32, i32* %A
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ret i32 %V
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}
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; "if then"
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define void @test5(i1 %C, i32* %P) {
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; CHECK-LABEL: @test5(
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; CHECK-NEXT: br i1 [[C:%.*]], label [[COND:%.*]], label [[CONT:%.*]]
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; CHECK: Cond:
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; CHECK-NEXT: br label [[CONT]]
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; CHECK: Cont:
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; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i32 [ -987654321, [[COND]] ], [ 47, [[TMP0:%.*]] ]
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; CHECK-NEXT: store i32 [[STOREMERGE]], i32* [[P:%.*]], align 1
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; CHECK-NEXT: ret void
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;
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store i32 47, i32* %P, align 1
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br i1 %C, label %Cond, label %Cont
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Cond:
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store i32 -987654321, i32* %P, align 1
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br label %Cont
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Cont:
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ret void
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}
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; PR14753 - merging two stores should preserve the TBAA tag.
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define void @test6(i32 %n, float* %a, i32* %gi) nounwind uwtable ssp {
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; CHECK-LABEL: @test6(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[FOR_COND:%.*]]
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; CHECK: for.cond:
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; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i32 [ 42, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[FOR_BODY:%.*]] ]
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; CHECK-NEXT: store i32 [[STOREMERGE]], i32* [[GI:%.*]], align 4, !tbaa [[TBAA0:![0-9]+]]
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[STOREMERGE]], [[N:%.*]]
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; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[STOREMERGE]] to i64
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[A:%.*]], i64 [[IDXPROM]]
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; CHECK-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !tbaa [[TBAA4:![0-9]+]]
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[GI]], align 4, !tbaa [[TBAA0]]
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; CHECK-NEXT: [[INC]] = add nsw i32 [[TMP0]], 1
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; CHECK-NEXT: br label [[FOR_COND]]
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; CHECK: for.end:
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; CHECK-NEXT: ret void
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;
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entry:
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store i32 42, i32* %gi, align 4, !tbaa !0
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br label %for.cond
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for.cond:
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%storemerge = phi i32 [ 0, %entry ], [ %inc, %for.body ]
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%0 = load i32, i32* %gi, align 4, !tbaa !0
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%cmp = icmp slt i32 %0, %n
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br i1 %cmp, label %for.body, label %for.end
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for.body:
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%idxprom = sext i32 %0 to i64
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%arrayidx = getelementptr inbounds float, float* %a, i64 %idxprom
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store float 0.000000e+00, float* %arrayidx, align 4, !tbaa !3
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%1 = load i32, i32* %gi, align 4, !tbaa !0
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%inc = add nsw i32 %1, 1
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store i32 %inc, i32* %gi, align 4, !tbaa !0
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br label %for.cond
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for.end:
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ret void
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}
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define void @dse1(i32* %p) {
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; CHECK-LABEL: @dse1(
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; CHECK-NEXT: store i32 0, i32* [[P:%.*]], align 4
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; CHECK-NEXT: ret void
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;
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store i32 0, i32* %p
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store i32 0, i32* %p
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ret void
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}
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; Slightly subtle: if we're mixing atomic and non-atomic access to the
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; same location, then the contents of the location are undefined if there's
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; an actual race. As such, we're free to pick either store under the
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; assumption that we're not racing with any other thread.
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define void @dse2(i32* %p) {
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; CHECK-LABEL: @dse2(
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; CHECK-NEXT: store i32 0, i32* [[P:%.*]], align 4
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; CHECK-NEXT: ret void
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;
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store atomic i32 0, i32* %p unordered, align 4
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store i32 0, i32* %p
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ret void
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}
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define void @dse3(i32* %p) {
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; CHECK-LABEL: @dse3(
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; CHECK-NEXT: store atomic i32 0, i32* [[P:%.*]] unordered, align 4
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; CHECK-NEXT: ret void
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;
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store i32 0, i32* %p
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store atomic i32 0, i32* %p unordered, align 4
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ret void
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}
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define void @dse4(i32* %p) {
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; CHECK-LABEL: @dse4(
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; CHECK-NEXT: store atomic i32 0, i32* [[P:%.*]] unordered, align 4
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; CHECK-NEXT: ret void
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;
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store atomic i32 0, i32* %p unordered, align 4
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store atomic i32 0, i32* %p unordered, align 4
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ret void
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}
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; Implementation limit - could remove unordered store here, but
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; currently don't.
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define void @dse5(i32* %p) {
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; CHECK-LABEL: @dse5(
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; CHECK-NEXT: store atomic i32 0, i32* [[P:%.*]] unordered, align 4
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; CHECK-NEXT: store atomic i32 0, i32* [[P]] seq_cst, align 4
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; CHECK-NEXT: ret void
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;
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store atomic i32 0, i32* %p unordered, align 4
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store atomic i32 0, i32* %p seq_cst, align 4
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ret void
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}
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define void @write_back1(i32* %p) {
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; CHECK-LABEL: @write_back1(
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; CHECK-NEXT: ret void
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;
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%v = load i32, i32* %p
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store i32 %v, i32* %p
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ret void
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}
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define void @write_back2(i32* %p) {
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; CHECK-LABEL: @write_back2(
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; CHECK-NEXT: ret void
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;
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%v = load atomic i32, i32* %p unordered, align 4
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store i32 %v, i32* %p
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ret void
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}
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define void @write_back3(i32* %p) {
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; CHECK-LABEL: @write_back3(
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; CHECK-NEXT: ret void
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;
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%v = load i32, i32* %p
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store atomic i32 %v, i32* %p unordered, align 4
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ret void
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}
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define void @write_back4(i32* %p) {
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; CHECK-LABEL: @write_back4(
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; CHECK-NEXT: ret void
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;
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%v = load atomic i32, i32* %p unordered, align 4
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store atomic i32 %v, i32* %p unordered, align 4
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ret void
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}
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; Can't remove store due to ordering side effect
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define void @write_back5(i32* %p) {
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; CHECK-LABEL: @write_back5(
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; CHECK-NEXT: [[V:%.*]] = load atomic i32, i32* [[P:%.*]] unordered, align 4
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; CHECK-NEXT: store atomic i32 [[V]], i32* [[P]] seq_cst, align 4
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; CHECK-NEXT: ret void
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;
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%v = load atomic i32, i32* %p unordered, align 4
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store atomic i32 %v, i32* %p seq_cst, align 4
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ret void
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}
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define void @write_back6(i32* %p) {
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; CHECK-LABEL: @write_back6(
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; CHECK-NEXT: [[V:%.*]] = load atomic i32, i32* [[P:%.*]] seq_cst, align 4
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; CHECK-NEXT: ret void
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;
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%v = load atomic i32, i32* %p seq_cst, align 4
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store atomic i32 %v, i32* %p unordered, align 4
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ret void
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}
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define void @write_back7(i32* %p) {
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; CHECK-LABEL: @write_back7(
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; CHECK-NEXT: [[V:%.*]] = load atomic volatile i32, i32* [[P:%.*]] seq_cst, align 4
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; CHECK-NEXT: ret void
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;
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%v = load atomic volatile i32, i32* %p seq_cst, align 4
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store atomic i32 %v, i32* %p unordered, align 4
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ret void
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}
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@Unknown = external constant i32
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define void @store_to_constant() {
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; CHECK-LABEL: @store_to_constant(
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; CHECK-NEXT: ret void
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;
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store i32 0, i32* @Unknown
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ret void
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}
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!0 = !{!4, !4, i64 0}
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!1 = !{!"omnipotent char", !2}
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!2 = !{!"Simple C/C++ TBAA"}
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!3 = !{!"float", !1}
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!4 = !{!"int", !1}
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