eaf48dd9b0
Try to simplify BranchOnCount to `BranchOnCond true` if TC <= UF * VF. This is an alternative to D121899 which simplifies the VPlan directly instead of doing so late in code-gen. The potential benefit of doing this in VPlan is that this may help cost-modeling in the future. The reason this is done in prepareToExecute at the moment is that a single plan may be used for multiple VFs/UFs. There are further simplifications that can be applied as follow ups: 1. Replace inductions with constants 2. Replace vector region with regular block. Fixes #55354. Depends on D126679. Reviewed By: Ayal Differential Revision: https://reviews.llvm.org/D126680
73 lines
3.8 KiB
LLVM
73 lines
3.8 KiB
LLVM
; RUN: opt -loop-vectorize -S < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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define void @trip7_i64(i64* noalias nocapture noundef %dst, i64* noalias nocapture noundef readonly %src) #0 {
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; CHECK-LABEL: @trip7_i64(
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %vector.ph ], [ [[INDEX_NEXT:%.*]], %vector.body ]
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; CHECK: [[ACTIVE_LANE_MASK:%.*]] = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i64(i64 {{%.*}}, i64 7)
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; CHECK: {{%.*}} = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64.p0nxv2i64(<vscale x 2 x i64>* {{%.*}}, i32 8, <vscale x 2 x i1> [[ACTIVE_LANE_MASK]], <vscale x 2 x i64> poison)
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; CHECK: {{%.*}} = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64.p0nxv2i64(<vscale x 2 x i64>* {{%.*}}, i32 8, <vscale x 2 x i1> [[ACTIVE_LANE_MASK]], <vscale x 2 x i64> poison)
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; CHECK: call void @llvm.masked.store.nxv2i64.p0nxv2i64(<vscale x 2 x i64> {{%.*}}, <vscale x 2 x i64>* {{%.*}}, i32 8, <vscale x 2 x i1> [[ACTIVE_LANE_MASK]])
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; CHECK: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[VF:%.*]] = mul i64 [[VSCALE]], 2
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; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[VF]]
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; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[INDEX_NEXT]], {{%.*}}
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; CHECK-NEXT: br i1 [[COND]], label %middle.block, label %vector.body
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;
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%i.06 = phi i64 [ 0, %entry ], [ %inc, %for.body ]
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%arrayidx = getelementptr inbounds i64, i64* %src, i64 %i.06
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%0 = load i64, i64* %arrayidx, align 8
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%mul = shl nsw i64 %0, 1
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%arrayidx1 = getelementptr inbounds i64, i64* %dst, i64 %i.06
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%1 = load i64, i64* %arrayidx1, align 8
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%add = add nsw i64 %1, %mul
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store i64 %add, i64* %arrayidx1, align 8
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%inc = add nuw nsw i64 %i.06, 1
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%exitcond.not = icmp eq i64 %inc, 7
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br i1 %exitcond.not, label %for.end, label %for.body
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for.end: ; preds = %for.body
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ret void
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}
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define void @trip5_i8(i8* noalias nocapture noundef %dst, i8* noalias nocapture noundef readonly %src) #0 {
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; CHECK-LABEL: @trip5_i8(
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %vector.ph ], [ [[INDEX_NEXT:%.*]], %vector.body ]
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; CHECK: [[ACTIVE_LANE_MASK:%.*]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 {{%.*}}, i64 5)
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; CHECK: {{%.*}} = call <vscale x 16 x i8> @llvm.masked.load.nxv16i8.p0nxv16i8(<vscale x 16 x i8>* {{%.*}}, i32 1, <vscale x 16 x i1> [[ACTIVE_LANE_MASK]], <vscale x 16 x i8> poison)
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; CHECK: {{%.*}} = call <vscale x 16 x i8> @llvm.masked.load.nxv16i8.p0nxv16i8(<vscale x 16 x i8>* {{%.*}}, i32 1, <vscale x 16 x i1> [[ACTIVE_LANE_MASK]], <vscale x 16 x i8> poison)
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; CHECK: call void @llvm.masked.store.nxv16i8.p0nxv16i8(<vscale x 16 x i8> {{%.*}}, <vscale x 16 x i8>* {{%.*}}, i32 1, <vscale x 16 x i1> [[ACTIVE_LANE_MASK]])
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; CHECK: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[VF:%.*]] = mul i64 [[VSCALE]], 16
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; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[VF]]
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; CHECK-NEXT: br i1 true, label %middle.block, label %vector.body
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;
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%i.08 = phi i64 [ 0, %entry ], [ %inc, %for.body ]
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%arrayidx = getelementptr inbounds i8, i8* %src, i64 %i.08
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%0 = load i8, i8* %arrayidx, align 1
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%mul = shl i8 %0, 1
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%arrayidx1 = getelementptr inbounds i8, i8* %dst, i64 %i.08
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%1 = load i8, i8* %arrayidx1, align 1
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%add = add i8 %mul, %1
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store i8 %add, i8* %arrayidx1, align 1
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%inc = add nuw nsw i64 %i.08, 1
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%exitcond.not = icmp eq i64 %inc, 5
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br i1 %exitcond.not, label %for.end, label %for.body
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for.end: ; preds = %for.body
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ret void
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}
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attributes #0 = { vscale_range(1,16) "target-features"="+sve" }
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