defe11866a
The multiply part of FMA is commutable, but TargetSelectionDAG.td doesn't have it marked as commutable so tablegen won't automatically create the additional patterns. So manually add commuted patterns.
486 lines
14 KiB
LLVM
486 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IF %s
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; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64IF %s
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; These tests are each targeted at a particular RISC-V FPU instruction. Most
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; other files in this folder exercise LLVM IR instructions that don't directly
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; match a RISC-V instruction.
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define float @fadd_s(float %a, float %b) nounwind {
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; RV32IF-LABEL: fadd_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fadd.s ft0, ft1, ft0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fadd_s:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: fadd.s ft0, ft1, ft0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = fadd float %a, %b
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ret float %1
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}
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define float @fsub_s(float %a, float %b) nounwind {
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; RV32IF-LABEL: fsub_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fsub.s ft0, ft1, ft0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fsub_s:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: fsub.s ft0, ft1, ft0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = fsub float %a, %b
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ret float %1
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}
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define float @fmul_s(float %a, float %b) nounwind {
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; RV32IF-LABEL: fmul_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fmul.s ft0, ft1, ft0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fmul_s:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: fmul.s ft0, ft1, ft0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = fmul float %a, %b
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ret float %1
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}
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define float @fdiv_s(float %a, float %b) nounwind {
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; RV32IF-LABEL: fdiv_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fdiv.s ft0, ft1, ft0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fdiv_s:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: fdiv.s ft0, ft1, ft0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = fdiv float %a, %b
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ret float %1
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}
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declare float @llvm.sqrt.f32(float)
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define float @fsqrt_s(float %a) nounwind {
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; RV32IF-LABEL: fsqrt_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a0
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; RV32IF-NEXT: fsqrt.s ft0, ft0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fsqrt_s:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a0
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; RV64IF-NEXT: fsqrt.s ft0, ft0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = call float @llvm.sqrt.f32(float %a)
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ret float %1
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}
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declare float @llvm.copysign.f32(float, float)
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define float @fsgnj_s(float %a, float %b) nounwind {
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; RV32IF-LABEL: fsgnj_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fsgnj.s ft0, ft1, ft0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fsgnj_s:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: fsgnj.s ft0, ft1, ft0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = call float @llvm.copysign.f32(float %a, float %b)
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ret float %1
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}
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; This function performs extra work to ensure that
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; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
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define i32 @fneg_s(float %a, float %b) nounwind {
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; RV32IF-LABEL: fneg_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a0
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; RV32IF-NEXT: fadd.s ft0, ft0, ft0
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; RV32IF-NEXT: fneg.s ft1, ft0
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; RV32IF-NEXT: feq.s a0, ft0, ft1
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fneg_s:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a0
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; RV64IF-NEXT: fadd.s ft0, ft0, ft0
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; RV64IF-NEXT: fneg.s ft1, ft0
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; RV64IF-NEXT: feq.s a0, ft0, ft1
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; RV64IF-NEXT: ret
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%1 = fadd float %a, %a
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%2 = fneg float %1
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%3 = fcmp oeq float %1, %2
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%4 = zext i1 %3 to i32
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ret i32 %4
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}
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; This function performs extra work to ensure that
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; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
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define float @fsgnjn_s(float %a, float %b) nounwind {
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; RV32IF-LABEL: fsgnjn_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fadd.s ft0, ft1, ft0
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; RV32IF-NEXT: fsgnjn.s ft0, ft1, ft0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fsgnjn_s:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: fadd.s ft0, ft1, ft0
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; RV64IF-NEXT: fsgnjn.s ft0, ft1, ft0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = fadd float %a, %b
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%2 = fneg float %1
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%3 = call float @llvm.copysign.f32(float %a, float %2)
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ret float %3
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}
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declare float @llvm.fabs.f32(float)
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; This function performs extra work to ensure that
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; DAGCombiner::visitBITCAST doesn't replace the fabs with an and.
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define float @fabs_s(float %a, float %b) nounwind {
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; RV32IF-LABEL: fabs_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fadd.s ft0, ft1, ft0
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; RV32IF-NEXT: fabs.s ft1, ft0
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; RV32IF-NEXT: fadd.s ft0, ft1, ft0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fabs_s:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: fadd.s ft0, ft1, ft0
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; RV64IF-NEXT: fabs.s ft1, ft0
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; RV64IF-NEXT: fadd.s ft0, ft1, ft0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = fadd float %a, %b
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%2 = call float @llvm.fabs.f32(float %1)
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%3 = fadd float %2, %1
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ret float %3
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}
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declare float @llvm.minnum.f32(float, float)
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define float @fmin_s(float %a, float %b) nounwind {
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; RV32IF-LABEL: fmin_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fmin.s ft0, ft1, ft0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fmin_s:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: fmin.s ft0, ft1, ft0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = call float @llvm.minnum.f32(float %a, float %b)
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ret float %1
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}
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declare float @llvm.maxnum.f32(float, float)
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define float @fmax_s(float %a, float %b) nounwind {
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; RV32IF-LABEL: fmax_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fmax.s ft0, ft1, ft0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fmax_s:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: fmax.s ft0, ft1, ft0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = call float @llvm.maxnum.f32(float %a, float %b)
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ret float %1
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}
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define i32 @feq_s(float %a, float %b) nounwind {
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; RV32IF-LABEL: feq_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: feq.s a0, ft1, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: feq_s:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: feq.s a0, ft1, ft0
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; RV64IF-NEXT: ret
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%1 = fcmp oeq float %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @flt_s(float %a, float %b) nounwind {
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; RV32IF-LABEL: flt_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: flt.s a0, ft1, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: flt_s:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: flt.s a0, ft1, ft0
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; RV64IF-NEXT: ret
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%1 = fcmp olt float %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fle_s(float %a, float %b) nounwind {
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; RV32IF-LABEL: fle_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fle.s a0, ft1, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fle_s:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: fle.s a0, ft1, ft0
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; RV64IF-NEXT: ret
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%1 = fcmp ole float %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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declare float @llvm.fma.f32(float, float, float)
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define float @fmadd_s(float %a, float %b, float %c) nounwind {
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; RV32IF-LABEL: fmadd_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a2
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; RV32IF-NEXT: fmv.w.x ft1, a1
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; RV32IF-NEXT: fmv.w.x ft2, a0
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; RV32IF-NEXT: fmadd.s ft0, ft2, ft1, ft0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fmadd_s:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a2
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; RV64IF-NEXT: fmv.w.x ft1, a1
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; RV64IF-NEXT: fmv.w.x ft2, a0
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; RV64IF-NEXT: fmadd.s ft0, ft2, ft1, ft0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = call float @llvm.fma.f32(float %a, float %b, float %c)
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ret float %1
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}
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define float @fmsub_s(float %a, float %b, float %c) nounwind {
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; RV32IF-LABEL: fmsub_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fmv.w.x ft2, a2
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; RV32IF-NEXT: fmv.w.x ft3, zero
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; RV32IF-NEXT: fadd.s ft2, ft2, ft3
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; RV32IF-NEXT: fmsub.s ft0, ft1, ft0, ft2
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fmsub_s:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: fmv.w.x ft2, a2
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; RV64IF-NEXT: fmv.w.x ft3, zero
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; RV64IF-NEXT: fadd.s ft2, ft2, ft3
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; RV64IF-NEXT: fmsub.s ft0, ft1, ft0, ft2
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%c_ = fadd float 0.0, %c ; avoid negation using xor
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%negc = fsub float -0.0, %c_
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%1 = call float @llvm.fma.f32(float %a, float %b, float %negc)
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ret float %1
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}
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define float @fnmadd_s(float %a, float %b, float %c) nounwind {
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; RV32IF-LABEL: fnmadd_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a2
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; RV32IF-NEXT: fmv.w.x ft2, a0
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; RV32IF-NEXT: fmv.w.x ft3, zero
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; RV32IF-NEXT: fadd.s ft2, ft2, ft3
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; RV32IF-NEXT: fadd.s ft1, ft1, ft3
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; RV32IF-NEXT: fnmadd.s ft0, ft2, ft0, ft1
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fnmadd_s:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a2
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; RV64IF-NEXT: fmv.w.x ft2, a0
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; RV64IF-NEXT: fmv.w.x ft3, zero
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; RV64IF-NEXT: fadd.s ft2, ft2, ft3
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; RV64IF-NEXT: fadd.s ft1, ft1, ft3
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; RV64IF-NEXT: fnmadd.s ft0, ft2, ft0, ft1
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%a_ = fadd float 0.0, %a
|
|
%c_ = fadd float 0.0, %c
|
|
%nega = fsub float -0.0, %a_
|
|
%negc = fsub float -0.0, %c_
|
|
%1 = call float @llvm.fma.f32(float %nega, float %b, float %negc)
|
|
ret float %1
|
|
}
|
|
|
|
define float @fnmadd_s_2(float %a, float %b, float %c) nounwind {
|
|
; RV32IF-LABEL: fnmadd_s_2:
|
|
; RV32IF: # %bb.0:
|
|
; RV32IF-NEXT: fmv.w.x ft0, a0
|
|
; RV32IF-NEXT: fmv.w.x ft1, a2
|
|
; RV32IF-NEXT: fmv.w.x ft2, a1
|
|
; RV32IF-NEXT: fmv.w.x ft3, zero
|
|
; RV32IF-NEXT: fadd.s ft2, ft2, ft3
|
|
; RV32IF-NEXT: fadd.s ft1, ft1, ft3
|
|
; RV32IF-NEXT: fnmadd.s ft0, ft0, ft2, ft1
|
|
; RV32IF-NEXT: fmv.x.w a0, ft0
|
|
; RV32IF-NEXT: ret
|
|
;
|
|
; RV64IF-LABEL: fnmadd_s_2:
|
|
; RV64IF: # %bb.0:
|
|
; RV64IF-NEXT: fmv.w.x ft0, a0
|
|
; RV64IF-NEXT: fmv.w.x ft1, a2
|
|
; RV64IF-NEXT: fmv.w.x ft2, a1
|
|
; RV64IF-NEXT: fmv.w.x ft3, zero
|
|
; RV64IF-NEXT: fadd.s ft2, ft2, ft3
|
|
; RV64IF-NEXT: fadd.s ft1, ft1, ft3
|
|
; RV64IF-NEXT: fnmadd.s ft0, ft0, ft2, ft1
|
|
; RV64IF-NEXT: fmv.x.w a0, ft0
|
|
; RV64IF-NEXT: ret
|
|
%b_ = fadd float 0.0, %b
|
|
%c_ = fadd float 0.0, %c
|
|
%negb = fsub float -0.0, %b_
|
|
%negc = fsub float -0.0, %c_
|
|
%1 = call float @llvm.fma.f32(float %a, float %negb, float %negc)
|
|
ret float %1
|
|
}
|
|
|
|
define float @fnmsub_s(float %a, float %b, float %c) nounwind {
|
|
; RV32IF-LABEL: fnmsub_s:
|
|
; RV32IF: # %bb.0:
|
|
; RV32IF-NEXT: fmv.w.x ft0, a2
|
|
; RV32IF-NEXT: fmv.w.x ft1, a1
|
|
; RV32IF-NEXT: fmv.w.x ft2, a0
|
|
; RV32IF-NEXT: fmv.w.x ft3, zero
|
|
; RV32IF-NEXT: fadd.s ft2, ft2, ft3
|
|
; RV32IF-NEXT: fnmsub.s ft0, ft2, ft1, ft0
|
|
; RV32IF-NEXT: fmv.x.w a0, ft0
|
|
; RV32IF-NEXT: ret
|
|
;
|
|
; RV64IF-LABEL: fnmsub_s:
|
|
; RV64IF: # %bb.0:
|
|
; RV64IF-NEXT: fmv.w.x ft0, a2
|
|
; RV64IF-NEXT: fmv.w.x ft1, a1
|
|
; RV64IF-NEXT: fmv.w.x ft2, a0
|
|
; RV64IF-NEXT: fmv.w.x ft3, zero
|
|
; RV64IF-NEXT: fadd.s ft2, ft2, ft3
|
|
; RV64IF-NEXT: fnmsub.s ft0, ft2, ft1, ft0
|
|
; RV64IF-NEXT: fmv.x.w a0, ft0
|
|
; RV64IF-NEXT: ret
|
|
%a_ = fadd float 0.0, %a
|
|
%nega = fsub float -0.0, %a_
|
|
%1 = call float @llvm.fma.f32(float %nega, float %b, float %c)
|
|
ret float %1
|
|
}
|
|
|
|
define float @fnmsub_s_2(float %a, float %b, float %c) nounwind {
|
|
; RV32IF-LABEL: fnmsub_s_2:
|
|
; RV32IF: # %bb.0:
|
|
; RV32IF-NEXT: fmv.w.x ft0, a2
|
|
; RV32IF-NEXT: fmv.w.x ft1, a0
|
|
; RV32IF-NEXT: fmv.w.x ft2, a1
|
|
; RV32IF-NEXT: fmv.w.x ft3, zero
|
|
; RV32IF-NEXT: fadd.s ft2, ft2, ft3
|
|
; RV32IF-NEXT: fnmsub.s ft0, ft1, ft2, ft0
|
|
; RV32IF-NEXT: fmv.x.w a0, ft0
|
|
; RV32IF-NEXT: ret
|
|
;
|
|
; RV64IF-LABEL: fnmsub_s_2:
|
|
; RV64IF: # %bb.0:
|
|
; RV64IF-NEXT: fmv.w.x ft0, a2
|
|
; RV64IF-NEXT: fmv.w.x ft1, a0
|
|
; RV64IF-NEXT: fmv.w.x ft2, a1
|
|
; RV64IF-NEXT: fmv.w.x ft3, zero
|
|
; RV64IF-NEXT: fadd.s ft2, ft2, ft3
|
|
; RV64IF-NEXT: fnmsub.s ft0, ft1, ft2, ft0
|
|
; RV64IF-NEXT: fmv.x.w a0, ft0
|
|
; RV64IF-NEXT: ret
|
|
%b_ = fadd float 0.0, %b
|
|
%negb = fsub float -0.0, %b_
|
|
%1 = call float @llvm.fma.f32(float %a, float %negb, float %c)
|
|
ret float %1
|
|
}
|