caio/clang-p2996
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
160f85794de398bf488edf6b97c0bc1eb5754c80
clang-p2996/llvm/test/CodeGen/NVPTX
History
Artem Belevich 0ae8590354 [NVPTX, CUDA] Added support for m8n32k16 and m32n8k16 variants of wmma instructions. 
The new instructions were added added for sm_70+ GPUs in CUDA-9.1.

Differential Revision: https://reviews.llvm.org/D45068

llvm-svn: 330296
2018-04-18 21:51:48 +00:00
..
access-non-generic.ll
[NVPTX] Use addrspacecast instead of target-specific intrinsics in NVPTXGenericToNVVM.
2018-02-28 23:57:48 +00:00
add-128bit.ll
[DAGCombiner] add missing folds for scalar select of {-1,0,1}
2017-02-24 17:17:33 +00:00
addrspacecast-gvar.ll
…
addrspacecast.ll
…
aggr-param.ll
…
aggregate-return.ll
[NVPTX] Unify vectorization of load/stores of aggregate arguments and return values.
2017-02-21 22:56:05 +00:00
alias.ll
…
annotations.ll
…
arg-lowering.ll
…
arithmetic-fp-sm20.ll
…
arithmetic-int.ll
…
atomics-sm60.ll
[NVPTX] Implement __nvvm_atom_add_gen_d builtin.
2017-11-07 22:10:54 +00:00
atomics-with-scope.ll
…
atomics.ll
…
barrier.ll
[NVPTX] Implemented bar.warp.sync, barrier.sync, and vote{.sync} instructions/intrinsics/builtins.
2017-09-21 18:44:49 +00:00
bfe.ll
…
branch-fold.ll
…
bug17709.ll
[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
2017-05-15 17:17:44 +00:00
bug21465.ll
…
bug22246.ll
…
bug22322.ll
Add address space mangling to lifetime intrinsics
2017-04-10 20:18:21 +00:00
bug26185-2.ll
…
bug26185.ll
…
bypass-div.ll
…
call-with-alloca-buffer.ll
…
callchain.ll
…
calling-conv.ll
…
combine-min-max.ll
[NVPTX] Implement min/max in tablegen, rather than with custom DAGComine logic.
2017-01-18 00:09:01 +00:00
compare-int.ll
…
constant-vectors.ll
…
convergent-mir-call.ll
…
convert-fp.ll
…
convert-int-sm20.ll
…
ctlz.ll
[NVPTX] Don't flag StoreRetVal memory chain operands as ReadMem (PR32146)
2017-05-12 19:56:43 +00:00
ctpop.ll
[NVPTX] Don't flag StoreRetVal memory chain operands as ReadMem (PR32146)
2017-05-12 19:56:43 +00:00
cttz.ll
[NVPTX] Don't flag StoreRetVal memory chain operands as ReadMem (PR32146)
2017-05-12 19:56:43 +00:00
disable-opt.ll
…
div-ri.ll
…
divrem-combine.ll
…
envreg.ll
…
extloadv.ll
…
f16-instructions.ll
[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
2017-05-15 17:17:44 +00:00
f16x2-instructions.ll
[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
2017-05-15 17:17:44 +00:00
fast-math.ll
[NVPTX] Enable combineRepeatedFPDivisors for NVPTX.
2017-02-03 15:13:50 +00:00
fcos-no-fast-math.ll
…
fma-assoc.ll
[DAGCombine] require UnsafeFPMath for re-association of addition
2017-01-31 14:35:37 +00:00
fma-disable.ll
…
fma.ll
[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
2017-05-15 17:17:44 +00:00
fns.ll
[NVPTX,CUDA] Added llvm.nvvm.fns intrinsic and matching __nvvm_fns builtin in clang.
2017-12-06 17:50:05 +00:00
fp16.ll
…
fp-contract.ll
…
fp-literals.ll
…
fsin-no-fast-math.ll
…
function-align.ll
…
generic-to-nvvm-ir.ll
[NVPTX] Use addrspacecast instead of target-specific intrinsics in NVPTXGenericToNVVM.
2018-02-28 23:57:48 +00:00
generic-to-nvvm.ll
[NVPTX] Use addrspacecast instead of target-specific intrinsics in NVPTXGenericToNVVM.
2018-02-28 23:57:48 +00:00
global-addrspace.ll
…
global-ctor-empty.ll
…
global-ctor.ll
…
global-dtor.ll
…
global-ordering.ll
…
global-variable-big.ll
[NVPTX] Support global variables of integer type larger than i64.
2017-01-18 00:29:53 +00:00
global-visibility.ll
…
globals_init.ll
…
globals_lowering.ll
…
gvar-init.ll
…
half.ll
[NVPTX] add support for initializing fp16 arrays.
2018-04-06 22:25:08 +00:00
i1-global.ll
…
i1-int-to-fp.ll
…
i1-param.ll
…
i8-param.ll
[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
2017-05-15 17:17:44 +00:00
i128-global.ll
[NVPTX] Add lowering of i128 params.
2017-07-20 21:16:03 +00:00
i128-param.ll
[NVPTX] Add lowering of i128 params.
2017-07-20 21:16:03 +00:00
i128-retval.ll
[NVPTX] Add lowering of i128 params.
2017-07-20 21:16:03 +00:00
idioms.ll
[NVPTX] Lower integer absolute value idiom to abs instruction.
2017-01-18 00:08:44 +00:00
imad.ll
…
implicit-def.ll
…
inline-asm.ll
…
intrin-nocapture.ll
…
intrinsic-old.ll
…
intrinsics.ll
Fix some broken CHECK lines.
2017-01-22 20:28:56 +00:00
isspacep.ll
…
ld-addrspace.ll
…
ld-generic.ll
…
ld-st-addrrspace.py
[NVPTX] allow address space inference for volatile loads/stores.
2017-10-24 20:31:44 +00:00
ldg-invariant.ll
[NVPTX] Fixed vectorized LDG for f16.
2018-04-06 21:10:24 +00:00
ldparam-v4.ll
[NVPTX] Unify vectorization of load/stores of aggregate arguments and return values.
2017-02-21 22:56:05 +00:00
ldu-i8.ll
…
ldu-ldg.ll
…
ldu-reg-plus-offset.ll
…
lit.local.cfg
…
load-sext-i1.ll
…
load-with-non-coherent-cache.ll
…
LoadStoreVectorizer.ll
[NVPTX] Added support for .f16x2 instructions.
2017-02-23 22:38:24 +00:00
local-stack-frame.ll
…
loop-vectorize.ll
…
lower-aggr-copies.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
lower-alloca.ll
NVPTX: Move InferAddressSpaces to generic code
2017-01-31 01:10:58 +00:00
lower-kernel-ptr-arg.ll
…
machine-sink.ll
…
MachineSink-call.ll
…
MachineSink-convergent.ll
…
managed.ll
…
match.ll
[NVPTX] added match.{any,all}.sync instructions, intrinsics & builtins.
2017-09-26 17:07:23 +00:00
math-intrins.ll
…
minmax-negative.ll
Improve clamp recognition in ValueTracking.
2017-10-27 20:53:41 +00:00
misaligned-vector-ldst.ll
[NVPTX] Fixed lowering of unaligned loads/stores of f16 scalars and vectors.
2017-03-07 20:33:38 +00:00
module-inline-asm.ll
…
mulwide.ll
…
named-barriers.ll
[NVPTX] Add intrinsics to support named barriers.
2017-01-28 16:38:15 +00:00
noduplicate-syncthreads.ll
…
nounroll.ll
…
nvcl-param-align.ll
…
nvvm-reflect-module-flag.ll
…
nvvm-reflect.ll
…
param-align.ll
…
param-load-store.ll
[DAGCombiner] When combining zero_extend of a truncate, only mask before extending for vectors.
2018-03-01 22:32:25 +00:00
pr13291-i1-store.ll
…
pr16278.ll
…
pr17529.ll
…
read-global-variable-constant.ll
[NVPTX] Lower loads from global constants using ld.global.nc (aka LDG).
2018-02-28 23:58:05 +00:00
refl1.ll
…
reg-copy.ll
…
reg-types.ll
…
rotate.ll
…
sched1.ll
Only enable LiveRangeShrink for x86.
2017-05-17 20:18:13 +00:00
sched2.ll
Only enable LiveRangeShrink for x86.
2017-05-17 20:18:13 +00:00
sext-in-reg.ll
…
sext-params.ll
…
shfl-sync.ll
[NVPTX] Implemented shfl.sync instruction and supporting intrinsics/builtins.
2017-09-20 21:23:07 +00:00
shfl.ll
…
shift-parts.ll
…
simple-call.ll
[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
2017-05-15 17:17:44 +00:00
sm-version-20.ll
…
sm-version-21.ll
…
sm-version-30.ll
…
sm-version-32.ll
…
sm-version-35.ll
…
sm-version-37.ll
…
sm-version-50.ll
…
sm-version-52.ll
…
sm-version-53.ll
…
sm-version-60.ll
…
sm-version-61.ll
…
sm-version-62.ll
…
sm-version-70.ll
[CUDA] Added rudimentary support for CUDA-9 and sm_70.
2017-09-07 18:14:32 +00:00
speculative-execution-divergent-target.ll
…
sqrt-approx.ll
[NVPTX] Compute approx sqrt as 1/rsqrt(x) rather than x*rsqrt(x).
2017-01-31 23:08:57 +00:00
st-addrspace.ll
…
st-generic.ll
…
surf-read-cuda.ll
…
surf-read.ll
…
surf-write-cuda.ll
…
surf-write.ll
…
symbol-naming.ll
[NVPTX] Assign valid global names
2017-12-04 14:19:33 +00:00
TailDuplication-convergent.ll
…
tex-read-cuda.ll
…
tex-read.ll
…
texsurf-queries.ll
…
tid-range.ll
…
tuple-literal.ll
…
vec8.ll
Revert r302938 "Add LiveRangeShrink pass to shrink live range within BB."
2017-05-18 18:50:05 +00:00
vec-param-load.ll
[NVPTX] Unify vectorization of load/stores of aggregate arguments and return values.
2017-02-21 22:56:05 +00:00
vector-args.ll
…
vector-call.ll
[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
2017-05-15 17:17:44 +00:00
vector-compare.ll
…
vector-global.ll
…
vector-loads.ll
…
vector-select.ll
…
vector-stores.ll
…
vote.ll
[NVPTX] Implemented bar.warp.sync, barrier.sync, and vote{.sync} instructions/intrinsics/builtins.
2017-09-21 18:44:49 +00:00
weak-global.ll
…
weak-linkage.ll
…
wmma.py
[NVPTX, CUDA] Added support for m8n32k16 and m32n8k16 variants of wmma instructions.
2018-04-18 21:51:48 +00:00
zero-cs.ll
…
zeroext-32bit.ll
[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
2017-05-15 17:17:44 +00:00