9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
52 lines
2.2 KiB
LLVM
52 lines
2.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX908 %s
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; Make sure there are no v_accvgpr_read_b32 copying back and forth
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; between AGPR and VGPR.
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define amdgpu_kernel void @remat_constant_voids_spill(ptr addrspace(1) %p) #1 {
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; GFX908-LABEL: remat_constant_voids_spill:
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; GFX908: ; %bb.0:
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; GFX908-NEXT: v_accvgpr_write_b32 a1, 1
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; GFX908-NEXT: v_accvgpr_write_b32 a5, 6
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; GFX908-NEXT: v_accvgpr_write_b32 a6, 7
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; GFX908-NEXT: v_accvgpr_write_b32 a7, 8
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; GFX908-NEXT: v_accvgpr_write_b32 a0, 9
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; GFX908-NEXT: v_accvgpr_write_b32 a2, 2
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; GFX908-NEXT: v_accvgpr_write_b32 a3, 3
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; GFX908-NEXT: v_accvgpr_write_b32 a4, 4
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; GFX908-NEXT: ;;#ASMSTART
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; GFX908-NEXT: ;;#ASMEND
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; GFX908-NEXT: v_accvgpr_write_b32 a1, 5
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; GFX908-NEXT: ;;#ASMSTART
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; GFX908-NEXT: ;;#ASMEND
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; GFX908-NEXT: s_endpgm
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call void asm sideeffect "", "a,a,a,a"(i32 1, i32 2, i32 3, i32 4)
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call void asm sideeffect "", "a,a,a,a,a"(i32 5, i32 6, i32 7, i32 8, i32 9)
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ret void
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}
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define void @remat_regcopy_avoids_spill(i32 %v0, i32 %v1, i32 %v2, i32 %v3, i32 %v4, i32 %v5, i32 %v6, i32 %v7, i32 %v8, i32 %v9, i32 %v10) #1 {
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; GFX908-LABEL: remat_regcopy_avoids_spill:
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; GFX908: ; %bb.0:
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; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX908-NEXT: v_accvgpr_write_b32 a2, v0
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; GFX908-NEXT: v_accvgpr_write_b32 a3, v1
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; GFX908-NEXT: v_accvgpr_write_b32 a4, v2
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; GFX908-NEXT: v_accvgpr_write_b32 a0, v7
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; GFX908-NEXT: v_accvgpr_write_b32 a1, v8
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; GFX908-NEXT: v_accvgpr_write_b32 a5, v3
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; GFX908-NEXT: ;;#ASMSTART
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; GFX908-NEXT: ;;#ASMEND
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; GFX908-NEXT: v_accvgpr_write_b32 a2, v4
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; GFX908-NEXT: v_accvgpr_write_b32 a3, v5
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; GFX908-NEXT: v_accvgpr_write_b32 a4, v6
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; GFX908-NEXT: ;;#ASMSTART
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; GFX908-NEXT: ;;#ASMEND
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; GFX908-NEXT: s_setpc_b64 s[30:31]
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call void asm sideeffect "", "a,a,a,a"(i32 %v0, i32 %v1, i32 %v2, i32 %v3)
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call void asm sideeffect "", "a,a,a,a,a"(i32 %v4, i32 %v5, i32 %v6, i32 %v7, i32 %v8)
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ret void
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}
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attributes #1 = { nounwind "amdgpu-num-vgpr"="8" }
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