9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
94 lines
3.9 KiB
LLVM
94 lines
3.9 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; The bitcast should be pushed through the bitcasts so the vectors can
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; be broken down and the shared components can be CSEd
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; GCN-LABEL: {{^}}store_bitcast_constant_v8i32_to_v8f32:
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; GCN: buffer_store_dwordx4
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; GCN: buffer_store_dwordx4
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; GCN-NOT: v_mov_b32
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; GCN: buffer_store_dwordx4
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; GCN-NOT: v_mov_b32
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; GCN: buffer_store_dwordx4
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define amdgpu_kernel void @store_bitcast_constant_v8i32_to_v8f32(ptr addrspace(1) %out, <8 x i32> %vec) {
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%vec0.bc = bitcast <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 8> to <8 x float>
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store volatile <8 x float> %vec0.bc, ptr addrspace(1) %out
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%vec1.bc = bitcast <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 9> to <8 x float>
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store volatile <8 x float> %vec1.bc, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}store_bitcast_constant_v4i64_to_v8f32:
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; GCN: buffer_store_dwordx4
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; GCN: buffer_store_dwordx4
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; GCN-NOT: v_mov_b32
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; GCN: buffer_store_dwordx4
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; GCN-NOT: v_mov_b32
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; GCN: buffer_store_dwordx4
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define amdgpu_kernel void @store_bitcast_constant_v4i64_to_v8f32(ptr addrspace(1) %out, <4 x i64> %vec) {
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%vec0.bc = bitcast <4 x i64> <i64 7, i64 7, i64 7, i64 8> to <8 x float>
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store volatile <8 x float> %vec0.bc, ptr addrspace(1) %out
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%vec1.bc = bitcast <4 x i64> <i64 7, i64 7, i64 7, i64 9> to <8 x float>
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store volatile <8 x float> %vec1.bc, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}store_bitcast_constant_v4i64_to_v4f64:
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; GCN: buffer_store_dwordx4
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; GCN: buffer_store_dwordx4
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; GCN-NOT: v_mov_b32
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; GCN: buffer_store_dwordx4
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; GCN-NOT: v_mov_b32
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; GCN: buffer_store_dwordx4
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define amdgpu_kernel void @store_bitcast_constant_v4i64_to_v4f64(ptr addrspace(1) %out, <4 x i64> %vec) {
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%vec0.bc = bitcast <4 x i64> <i64 7, i64 7, i64 7, i64 8> to <4 x double>
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store volatile <4 x double> %vec0.bc, ptr addrspace(1) %out
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%vec1.bc = bitcast <4 x i64> <i64 7, i64 7, i64 7, i64 9> to <4 x double>
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store volatile <4 x double> %vec1.bc, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}store_bitcast_constant_v8i32_to_v16i16:
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; GCN: buffer_store_dwordx4
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; GCN: buffer_store_dwordx4
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; GCN-NOT: v_mov_b32
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; GCN: buffer_store_dwordx4
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; GCN-NOT: v_mov_b32
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; GCN: buffer_store_dwordx4
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define amdgpu_kernel void @store_bitcast_constant_v8i32_to_v16i16(ptr addrspace(1) %out, <16 x i16> %vec) {
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%vec0.bc = bitcast <16 x i16> <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 8> to <8 x float>
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store volatile <8 x float> %vec0.bc, ptr addrspace(1) %out
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%vec1.bc = bitcast <16 x i16> <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 9> to <8 x float>
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store volatile <8 x float> %vec1.bc, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}store_value_lowered_to_undef_bitcast_source:
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; GCN-NOT: store_dword
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define amdgpu_kernel void @store_value_lowered_to_undef_bitcast_source(ptr addrspace(1) %out, i64 %a, i64 %b) #0 {
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%undef = call i64 @llvm.amdgcn.icmp.i64(i64 %a, i64 %b, i32 999) #1
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%bc = bitcast i64 %undef to <2 x i32>
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store volatile <2 x i32> %bc, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}store_value_lowered_to_undef_bitcast_source_extractelt:
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; GCN-NOT: store_dword
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define amdgpu_kernel void @store_value_lowered_to_undef_bitcast_source_extractelt(ptr addrspace(1) %out, i64 %a, i64 %b) #0 {
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%undef = call i64 @llvm.amdgcn.icmp.i64(i64 %a, i64 %b, i32 9999) #1
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%bc = bitcast i64 %undef to <2 x i32>
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%elt1 = extractelement <2 x i32> %bc, i32 1
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store volatile i32 %elt1, ptr addrspace(1) %out
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ret void
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}
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declare i64 @llvm.amdgcn.icmp.i64(i64, i64, i32) #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone convergent }
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