9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
66 lines
2.2 KiB
LLVM
66 lines
2.2 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -print-after=si-annotate-control-flow %s -o /dev/null 2>&1 | FileCheck %s
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target datalayout = "n32"
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; CHECK-LABEL: @switch_unreachable_default
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define amdgpu_kernel void @switch_unreachable_default(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) #0 {
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centry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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switch i32 %tid, label %sw.default [
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i32 0, label %sw.bb0
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i32 1, label %sw.bb1
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]
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sw.bb0:
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br label %sw.epilog
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sw.bb1:
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br label %sw.epilog
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sw.default:
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unreachable
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sw.epilog:
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%ptr = phi ptr addrspace(1) [%in0, %sw.bb0], [%in1, %sw.bb1]
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br label %sw.while
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; The loop below is necessary to preserve the effect of the
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; unreachable default on divergence analysis in the presence of other
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; optimizations. The loop consists of a single block where the loop
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; exit is divergent because it depends on the divergent phi at the
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; start of the block. The checks below ensure that the loop exit is
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; handled correctly as divergent. But the data-flow within the block
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; is sensitive to optimizations; so we just ensure that the relevant
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; operations in the block body are indeed in the same block.
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; CHECK: [[PHI:%[a-zA-Z0-9._]+]] = phi i64
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; CHECK-NOT: {{ br }}
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; CHECK: load i8
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; CHECK-NOT: {{ br }}
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; CHECK: [[ICMP:%[a-zA-Z0-9._]+]] = icmp eq
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; CHECK: [[IF:%[a-zA-Z0-9._]+]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[ICMP]], i64 [[PHI]])
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; CHECK: [[LOOP:%[a-zA-Z0-9._]+]] = call i1 @llvm.amdgcn.loop.i64(i64 [[IF]])
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; CHECK: br i1 [[LOOP]]
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sw.while:
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%p = phi ptr addrspace(1) [ %ptr, %sw.epilog ], [ %incdec.ptr, %sw.while ]
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%count = phi i32 [ 0, %sw.epilog ], [ %count.inc, %sw.while ]
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%char = load i8, ptr addrspace(1) %p, align 1
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%tobool = icmp eq i8 %char, 0
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%incdec.ptr = getelementptr inbounds i8, ptr addrspace(1) %p, i64 1
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%count.inc = add i32 %count, 1
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br i1 %tobool, label %sw.exit, label %sw.while
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sw.exit:
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%tid64 = zext i32 %tid to i64
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%gep_out = getelementptr inbounds i32, ptr addrspace(1) %out, i64 %tid64
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store i32 %count, ptr addrspace(1) %gep_out, align 4
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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attributes #0 = { nounwind readnone }
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attributes #1 = { convergent noinline optnone }
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