9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
99 lines
4.6 KiB
LLVM
99 lines
4.6 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN %s
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; GCN-LABEL: {{^}}test_fmaximum3_olt_0_f32:
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; GCN: buffer_load_b32 [[REGC:v[0-9]+]]
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; GCN: buffer_load_b32 [[REGB:v[0-9]+]]
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; GCN: buffer_load_b32 [[REGA:v[0-9]+]]
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; GCN: v_maximum3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
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; GCN: buffer_store_b32 [[RESULT]],
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define amdgpu_kernel void @test_fmaximum3_olt_0_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr, ptr addrspace(1) %cptr) {
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%a = load volatile float, ptr addrspace(1) %aptr, align 4
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%b = load volatile float, ptr addrspace(1) %bptr, align 4
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%c = load volatile float, ptr addrspace(1) %cptr, align 4
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%f0 = call float @llvm.maximum.f32(float %a, float %b)
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%f1 = call float @llvm.maximum.f32(float %f0, float %c)
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store float %f1, ptr addrspace(1) %out, align 4
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ret void
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}
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; Commute operand of second fmaximum
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; GCN-LABEL: {{^}}test_fmaximum3_olt_1_f32:
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; GCN: buffer_load_b32 [[REGB:v[0-9]+]]
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; GCN: buffer_load_b32 [[REGA:v[0-9]+]]
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; GCN: buffer_load_b32 [[REGC:v[0-9]+]]
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; GCN: v_maximum3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
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; GCN: buffer_store_b32 [[RESULT]],
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define amdgpu_kernel void @test_fmaximum3_olt_1_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr, ptr addrspace(1) %cptr) {
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%a = load volatile float, ptr addrspace(1) %aptr, align 4
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%b = load volatile float, ptr addrspace(1) %bptr, align 4
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%c = load volatile float, ptr addrspace(1) %cptr, align 4
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%f0 = call float @llvm.maximum.f32(float %a, float %b)
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%f1 = call float @llvm.maximum.f32(float %c, float %f0)
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store float %f1, ptr addrspace(1) %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_fmaximum3_olt_0_f16:
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; GCN: buffer_load_u16 [[REGC:v[0-9]+]]
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; GCN: buffer_load_u16 [[REGB:v[0-9]+]]
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; GCN: buffer_load_u16 [[REGA:v[0-9]+]]
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; GCN: v_maximum3_f16 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
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; GCN: buffer_store_b16 [[RESULT]],
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define amdgpu_kernel void @test_fmaximum3_olt_0_f16(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr, ptr addrspace(1) %cptr) {
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%a = load volatile half, ptr addrspace(1) %aptr, align 2
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%b = load volatile half, ptr addrspace(1) %bptr, align 2
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%c = load volatile half, ptr addrspace(1) %cptr, align 2
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%f0 = call half @llvm.maximum.f16(half %a, half %b)
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%f1 = call half @llvm.maximum.f16(half %f0, half %c)
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store half %f1, ptr addrspace(1) %out, align 2
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ret void
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}
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; GCN-LABEL: {{^}}test_fmaximum3_olt_1_f16:
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; GCN: buffer_load_u16 [[REGA:v[0-9]+]]
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; GCN: buffer_load_u16 [[REGB:v[0-9]+]]
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; GCN: buffer_load_u16 [[REGC:v[0-9]+]]
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; GCN: v_maximum3_f16 [[RESULT:v[0-9]+]], [[REGC]], [[REGA]], [[REGB]]
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; GCN: buffer_store_b16 [[RESULT]],
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define amdgpu_kernel void @test_fmaximum3_olt_1_f16(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr, ptr addrspace(1) %cptr) {
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%a = load volatile half, ptr addrspace(1) %aptr, align 2
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%b = load volatile half, ptr addrspace(1) %bptr, align 2
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%c = load volatile half, ptr addrspace(1) %cptr, align 2
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%f0 = call half @llvm.maximum.f16(half %a, half %b)
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%f1 = call half @llvm.maximum.f16(half %c, half %f0)
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store half %f1, ptr addrspace(1) %out, align 2
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ret void
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}
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; Checks whether the test passes; performMinMaxCombine() should not optimize vector patterns of maximum3
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; since there are no pack instructions for fmaximum3.
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; GCN-LABEL: {{^}}no_fmaximum3_v2f16:
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; GCN: v_pk_maximum_f16 v0, v0, v1
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; GCN: v_pk_maximum_f16 v0, v2, v0
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; GCN: v_pk_maximum_f16 v0, v0, v3
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; GCN-NEXT: s_setpc_b64
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define <2 x half> @no_fmaximum3_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d) {
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entry:
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%max = call <2 x half> @llvm.maximum.v2f16(<2 x half> %a, <2 x half> %b)
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%max1 = call <2 x half> @llvm.maximum.v2f16(<2 x half> %c, <2 x half> %max)
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%res = call <2 x half> @llvm.maximum.v2f16(<2 x half> %max1, <2 x half> %d)
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ret <2 x half> %res
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}
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; GCN-LABEL: {{^}}no_fmaximum3_olt_0_f64:
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; GCN-COUNT-2: v_maximum_f64
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define amdgpu_kernel void @no_fmaximum3_olt_0_f64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr, ptr addrspace(1) %cptr) {
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%a = load volatile double, ptr addrspace(1) %aptr, align 4
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%b = load volatile double, ptr addrspace(1) %bptr, align 4
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%c = load volatile double, ptr addrspace(1) %cptr, align 4
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%f0 = call double @llvm.maximum.f64(double %a, double %b)
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%f1 = call double @llvm.maximum.f64(double %f0, double %c)
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store double %f1, ptr addrspace(1) %out, align 4
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ret void
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}
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declare double @llvm.maximum.f64(double, double)
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declare float @llvm.maximum.f32(float, float)
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declare half @llvm.maximum.f16(half, half)
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declare <2 x half> @llvm.maximum.v2f16(<2 x half>, <2 x half>)
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