9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
61 lines
2.2 KiB
LLVM
61 lines
2.2 KiB
LLVM
; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}fneg_f64:
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; GCN: s_xor_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
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define amdgpu_kernel void @fneg_f64(ptr addrspace(1) %out, double %in) {
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%fneg = fsub double -0.000000e+00, %in
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store double %fneg, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}fneg_v2f64:
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; GCN: s_xor_b32
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; GCN: s_xor_b32
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define amdgpu_kernel void @fneg_v2f64(ptr addrspace(1) nocapture %out, <2 x double> %in) {
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%fneg = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %in
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store <2 x double> %fneg, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}fneg_v4f64:
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; R600: -PV
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; R600: -T
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; R600: -PV
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; R600: -PV
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; GCN: s_xor_b32
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; GCN: s_xor_b32
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; GCN: s_xor_b32
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; GCN: s_xor_b32
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define amdgpu_kernel void @fneg_v4f64(ptr addrspace(1) nocapture %out, <4 x double> %in) {
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%fneg = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %in
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store <4 x double> %fneg, ptr addrspace(1) %out
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ret void
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}
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; DAGCombiner will transform:
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; (fneg (f64 bitcast (i64 a))) => (f64 bitcast (xor (i64 a), 0x80000000))
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; unless the target returns true for isNegFree()
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; FUNC-LABEL: {{^}}fneg_free_f64:
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; GCN: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, -{{s\[[0-9]+:[0-9]+\]}}, 0{{$}}
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define amdgpu_kernel void @fneg_free_f64(ptr addrspace(1) %out, i64 %in) {
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%bc = bitcast i64 %in to double
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%fsub = fsub double 0.0, %bc
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store double %fsub, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}fneg_fold_f64:
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; SI: s_load_dwordx2 [[NEG_VALUE:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x13
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; VI: s_load_dwordx2 [[NEG_VALUE:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x4c
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; GCN-NOT: xor
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; GCN: v_mul_f64 {{v\[[0-9]+:[0-9]+\]}}, -[[NEG_VALUE]], [[NEG_VALUE]]
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define amdgpu_kernel void @fneg_fold_f64(ptr addrspace(1) %out, [8 x i32], double %in) {
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%fsub = fsub double -0.0, %in
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%fmul = fmul double %fsub, %in
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store double %fmul, ptr addrspace(1) %out
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ret void
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}
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