f93aa5157a
These generic targets include multiple GPUs and will, in the future, provide a way to build once and run on multiple GPU, at the cost of less optimization opportunities. Note that this is just doing the compiler side of things, device libs an runtimes/loader/etc. don't know about these targets yet, so none of them actually work in practice right now. This is just the initial commit to make LLVM aware of them. This contains the documentation changes for both this change and #76954 as well.
129 lines
5.2 KiB
LLVM
129 lines
5.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -amdgpu-atomic-optimizer-strategy=None -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx9-generic --amdhsa-code-object-version=6 -amdgpu-atomic-optimizer-strategy=None -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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@gds0 = internal addrspace(2) global [4 x i32] undef, align 4
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@lds0 = internal addrspace(3) global [4 x i32] undef, align 128
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@lds1 = internal addrspace(3) global [4 x i32] undef, align 256
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; These two objects should be allocated at the same constant offsets
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; from the base.
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define amdgpu_kernel void @alloc_lds_gds(ptr addrspace(1) %out) #1 {
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; GCN-LABEL: alloc_lds_gds:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_mov_b32_e32 v0, 5
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; GCN-NEXT: v_mov_b32_e32 v1, 0
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; GCN-NEXT: s_mov_b32 m0, 16
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; GCN-NEXT: s_nop 0
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; GCN-NEXT: ds_add_u32 v1, v0 offset:12 gds
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: buffer_wbinvl1
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; GCN-NEXT: ds_add_u32 v1, v0 offset:12
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_endpgm
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%gep.gds = getelementptr [4 x i32], ptr addrspace(2) @gds0, i32 0, i32 3
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%val0 = atomicrmw add ptr addrspace(2) %gep.gds, i32 5 acq_rel
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%gep.lds = getelementptr [4 x i32], ptr addrspace(3) @lds0, i32 0, i32 3
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%val1 = atomicrmw add ptr addrspace(3) %gep.lds, i32 5 acq_rel
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ret void
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}
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; The LDS alignment shouldn't change offset of GDS.
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define amdgpu_kernel void @alloc_lds_gds_align(ptr addrspace(1) %out) #1 {
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; GCN-LABEL: alloc_lds_gds_align:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_mov_b32_e32 v0, 5
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; GCN-NEXT: v_mov_b32_e32 v1, 0
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; GCN-NEXT: s_mov_b32 m0, 16
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; GCN-NEXT: s_nop 0
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; GCN-NEXT: ds_add_u32 v1, v0 offset:12 gds
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: buffer_wbinvl1
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; GCN-NEXT: ds_add_u32 v1, v0 offset:140
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: ds_add_u32 v1, v0 offset:12
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_endpgm
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%gep.gds = getelementptr [4 x i32], ptr addrspace(2) @gds0, i32 0, i32 3
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%val0 = atomicrmw add ptr addrspace(2) %gep.gds, i32 5 acq_rel
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%gep.lds0 = getelementptr [4 x i32], ptr addrspace(3) @lds0, i32 0, i32 3
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%val1 = atomicrmw add ptr addrspace(3) %gep.lds0, i32 5 acq_rel
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%gep.lds1 = getelementptr [4 x i32], ptr addrspace(3) @lds1, i32 0, i32 3
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%val2 = atomicrmw add ptr addrspace(3) %gep.lds1, i32 5 acq_rel
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ret void
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}
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@gds_align8 = internal addrspace(2) global [4 x i32] undef, align 8
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@gds_align32 = internal addrspace(2) global [4 x i32] undef, align 32
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define amdgpu_kernel void @gds_global_align(ptr addrspace(1) %out) {
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; GCN-LABEL: gds_global_align:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_mov_b32_e32 v0, 5
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; GCN-NEXT: v_mov_b32_e32 v1, 0
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; GCN-NEXT: s_mov_b32 m0, 32
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; GCN-NEXT: s_nop 0
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; GCN-NEXT: ds_add_u32 v1, v0 offset:28 gds
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: buffer_wbinvl1
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; GCN-NEXT: ds_add_u32 v1, v0 offset:12 gds
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: buffer_wbinvl1
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; GCN-NEXT: s_endpgm
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%gep.gds0 = getelementptr [4 x i32], ptr addrspace(2) @gds_align8, i32 0, i32 3
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%val0 = atomicrmw add ptr addrspace(2) %gep.gds0, i32 5 acq_rel
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%gep.gds1 = getelementptr [4 x i32], ptr addrspace(2) @gds_align32, i32 0, i32 3
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%val1 = atomicrmw add ptr addrspace(2) %gep.gds1, i32 5 acq_rel
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ret void
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}
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define amdgpu_kernel void @gds_global_align_plus_attr(ptr addrspace(1) %out) #0 {
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; GCN-LABEL: gds_global_align_plus_attr:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_mov_b32_e32 v0, 5
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; GCN-NEXT: v_mov_b32_e32 v1, 0
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; GCN-NEXT: s_movk_i32 m0, 0x420
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; GCN-NEXT: s_nop 0
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; GCN-NEXT: ds_add_u32 v1, v0 offset:1052 gds
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: buffer_wbinvl1
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; GCN-NEXT: ds_add_u32 v1, v0 offset:1036 gds
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: buffer_wbinvl1
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; GCN-NEXT: s_endpgm
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%gep.gds0 = getelementptr [4 x i32], ptr addrspace(2) @gds_align8, i32 0, i32 3
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%val0 = atomicrmw add ptr addrspace(2) %gep.gds0, i32 5 acq_rel
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%gep.gds1 = getelementptr [4 x i32], ptr addrspace(2) @gds_align32, i32 0, i32 3
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%val1 = atomicrmw add ptr addrspace(2) %gep.gds1, i32 5 acq_rel
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ret void
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}
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@small.gds = internal addrspace(2) global i8 undef, align 1
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@gds.external = external unnamed_addr addrspace(3) global [0 x i32], align 4
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define amdgpu_kernel void @gds_extern_align(ptr addrspace(1) %out, ptr addrspace(2) %gds.arg) #0 {
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; GCN-LABEL: gds_extern_align:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dword s0, s[0:1], 0x8
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; GCN-NEXT: v_mov_b32_e32 v0, 5
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; GCN-NEXT: s_movk_i32 m0, 0x401
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; GCN-NEXT: s_movk_i32 s1, 0x400
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: ; use s1
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; GCN-NEXT: ;;#ASMEND
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v1, s0
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; GCN-NEXT: ds_add_u32 v1, v0 offset:12 gds
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: buffer_wbinvl1
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; GCN-NEXT: s_endpgm
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call void asm sideeffect "; use $0","s"(ptr addrspace(2) @small.gds)
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%gep.gds0 = getelementptr [4 x i32], ptr addrspace(2) %gds.arg, i32 0, i32 3
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%val0 = atomicrmw add ptr addrspace(2) %gep.gds0, i32 5 acq_rel
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ret void
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}
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attributes #0 = { "amdgpu-gds-size"="1024" }
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