9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
25 lines
949 B
YAML
25 lines
949 B
YAML
# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -start-before=si-pre-emit-peephole %s -o - | FileCheck -check-prefix=GCN %s
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# Verify that the dedicated hazard recognizer pass is run after late peephole
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# optimizations. New hazards can be introduced if instructions are removed by
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# passes that are run before the final hazard recognizer.
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---
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# GCN-LABEL: {{^}}mai_hazard_pass_ordering_optimize_vcc_branch:
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# GCN: v_accvgpr_read_b32
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# GCN-NEXT: s_nop
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# GCN-NEXT: flat_load_dword
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name: mai_hazard_pass_ordering_optimize_vcc_branch
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body: |
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bb.0:
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$vgpr0 = V_MOV_B32_e32 1, implicit $exec
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$vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec
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$sgpr8_sgpr9 = S_MOV_B64 -1
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$vgpr3 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr
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$vcc = S_ANDN2_B64 $exec, killed renamable $sgpr8_sgpr9, implicit-def dead $scc
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S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc
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bb.1:
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S_ENDPGM 0
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...
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