9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
143 lines
8.0 KiB
LLVM
143 lines
8.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding | FileCheck -enable-var-scope -check-prefixes=PREGFX10-UNPACKED %s
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; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=PREGFX10-PACKED %s
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; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=PREGFX10-PACKED %s
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; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX10-PACKED %s
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; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX11-PACKED %s
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define amdgpu_ps half @tbuffer_load_d16_x(ptr addrspace(8) inreg %rsrc) {
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; PREGFX10-UNPACKED-LABEL: tbuffer_load_d16_x:
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; PREGFX10-UNPACKED: ; %bb.0: ; %main_body
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; PREGFX10-UNPACKED-NEXT: tbuffer_load_format_d16_x v0, off, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] ; encoding: [0x00,0x00,0xb4,0xe8,0x00,0x00,0x00,0x80]
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; PREGFX10-UNPACKED-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
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; PREGFX10-UNPACKED-NEXT: ; return to shader part epilog
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;
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; PREGFX10-PACKED-LABEL: tbuffer_load_d16_x:
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; PREGFX10-PACKED: ; %bb.0: ; %main_body
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; PREGFX10-PACKED-NEXT: tbuffer_load_format_d16_x v0, off, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
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; PREGFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
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; PREGFX10-PACKED-NEXT: ; return to shader part epilog
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;
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; GFX10-PACKED-LABEL: tbuffer_load_d16_x:
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; GFX10-PACKED: ; %bb.0: ; %main_body
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; GFX10-PACKED-NEXT: tbuffer_load_format_d16_x v0, off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
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; GFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
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; GFX10-PACKED-NEXT: ; return to shader part epilog
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;
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; GFX11-PACKED-LABEL: tbuffer_load_d16_x:
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; GFX11-PACKED: ; %bb.0: ; %main_body
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; GFX11-PACKED-NEXT: tbuffer_load_d16_format_x v0, off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
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; GFX11-PACKED-NEXT: s_waitcnt vmcnt(0)
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; GFX11-PACKED-NEXT: ; return to shader part epilog
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main_body:
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%data = call half @llvm.amdgcn.raw.ptr.tbuffer.load.f16(ptr addrspace(8) %rsrc, i32 0, i32 0, i32 22, i32 0)
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ret half %data
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}
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define amdgpu_ps half @tbuffer_load_d16_xy(ptr addrspace(8) inreg %rsrc) {
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; PREGFX10-UNPACKED-LABEL: tbuffer_load_d16_xy:
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; PREGFX10-UNPACKED: ; %bb.0: ; %main_body
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; PREGFX10-UNPACKED-NEXT: tbuffer_load_format_d16_xy v[0:1], off, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] ; encoding: [0x00,0x80,0xb4,0xe8,0x00,0x00,0x00,0x80]
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; PREGFX10-UNPACKED-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
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; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v0, v1 ; encoding: [0x01,0x03,0x00,0x7e]
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; PREGFX10-UNPACKED-NEXT: ; return to shader part epilog
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;
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; PREGFX10-PACKED-LABEL: tbuffer_load_d16_xy:
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; PREGFX10-PACKED: ; %bb.0: ; %main_body
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; PREGFX10-PACKED-NEXT: tbuffer_load_format_d16_xy v0, off, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
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; PREGFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
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; PREGFX10-PACKED-NEXT: v_lshrrev_b32_e32 v0, 16, v0
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; PREGFX10-PACKED-NEXT: ; return to shader part epilog
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;
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; GFX10-PACKED-LABEL: tbuffer_load_d16_xy:
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; GFX10-PACKED: ; %bb.0: ; %main_body
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; GFX10-PACKED-NEXT: tbuffer_load_format_d16_xy v0, off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
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; GFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
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; GFX10-PACKED-NEXT: v_lshrrev_b32_e32 v0, 16, v0
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; GFX10-PACKED-NEXT: ; return to shader part epilog
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;
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; GFX11-PACKED-LABEL: tbuffer_load_d16_xy:
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; GFX11-PACKED: ; %bb.0: ; %main_body
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; GFX11-PACKED-NEXT: tbuffer_load_d16_format_xy v0, off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
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; GFX11-PACKED-NEXT: s_waitcnt vmcnt(0)
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; GFX11-PACKED-NEXT: v_lshrrev_b32_e32 v0, 16, v0
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; GFX11-PACKED-NEXT: ; return to shader part epilog
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main_body:
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%data = call <2 x half> @llvm.amdgcn.raw.ptr.tbuffer.load.v2f16(ptr addrspace(8) %rsrc, i32 0, i32 0, i32 22, i32 0)
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%elt = extractelement <2 x half> %data, i32 1
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ret half %elt
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}
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define amdgpu_ps half @tbuffer_load_d16_xyz(ptr addrspace(8) inreg %rsrc) {
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; PREGFX10-UNPACKED-LABEL: tbuffer_load_d16_xyz:
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; PREGFX10-UNPACKED: ; %bb.0: ; %main_body
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; PREGFX10-UNPACKED-NEXT: tbuffer_load_format_d16_xyz v[0:2], off, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] ; encoding: [0x00,0x00,0xb5,0xe8,0x00,0x00,0x00,0x80]
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; PREGFX10-UNPACKED-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
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; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v0, v2 ; encoding: [0x02,0x03,0x00,0x7e]
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; PREGFX10-UNPACKED-NEXT: ; return to shader part epilog
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;
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; PREGFX10-PACKED-LABEL: tbuffer_load_d16_xyz:
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; PREGFX10-PACKED: ; %bb.0: ; %main_body
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; PREGFX10-PACKED-NEXT: tbuffer_load_format_d16_xyz v[0:1], off, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
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; PREGFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
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; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v0, v1
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; PREGFX10-PACKED-NEXT: ; return to shader part epilog
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;
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; GFX10-PACKED-LABEL: tbuffer_load_d16_xyz:
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; GFX10-PACKED: ; %bb.0: ; %main_body
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; GFX10-PACKED-NEXT: tbuffer_load_format_d16_xyz v[0:1], off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
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; GFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
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; GFX10-PACKED-NEXT: v_mov_b32_e32 v0, v1
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; GFX10-PACKED-NEXT: ; return to shader part epilog
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;
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; GFX11-PACKED-LABEL: tbuffer_load_d16_xyz:
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; GFX11-PACKED: ; %bb.0: ; %main_body
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; GFX11-PACKED-NEXT: tbuffer_load_d16_format_xyz v[0:1], off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
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; GFX11-PACKED-NEXT: s_waitcnt vmcnt(0)
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; GFX11-PACKED-NEXT: v_mov_b32_e32 v0, v1
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; GFX11-PACKED-NEXT: ; return to shader part epilog
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main_body:
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%data = call <3 x half> @llvm.amdgcn.raw.ptr.tbuffer.load.v3f16(ptr addrspace(8) %rsrc, i32 0, i32 0, i32 22, i32 0)
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%elt = extractelement <3 x half> %data, i32 2
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ret half %elt
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}
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define amdgpu_ps half @tbuffer_load_d16_xyzw(ptr addrspace(8) inreg %rsrc) {
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; PREGFX10-UNPACKED-LABEL: tbuffer_load_d16_xyzw:
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; PREGFX10-UNPACKED: ; %bb.0: ; %main_body
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; PREGFX10-UNPACKED-NEXT: tbuffer_load_format_d16_xyzw v[0:3], off, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] ; encoding: [0x00,0x80,0xb5,0xe8,0x00,0x00,0x00,0x80]
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; PREGFX10-UNPACKED-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
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; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v0, v3 ; encoding: [0x03,0x03,0x00,0x7e]
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; PREGFX10-UNPACKED-NEXT: ; return to shader part epilog
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;
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; PREGFX10-PACKED-LABEL: tbuffer_load_d16_xyzw:
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; PREGFX10-PACKED: ; %bb.0: ; %main_body
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; PREGFX10-PACKED-NEXT: tbuffer_load_format_d16_xyzw v[0:1], off, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
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; PREGFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
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; PREGFX10-PACKED-NEXT: v_lshrrev_b32_e32 v0, 16, v1
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; PREGFX10-PACKED-NEXT: ; return to shader part epilog
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;
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; GFX10-PACKED-LABEL: tbuffer_load_d16_xyzw:
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; GFX10-PACKED: ; %bb.0: ; %main_body
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; GFX10-PACKED-NEXT: tbuffer_load_format_d16_xyzw v[0:1], off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
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; GFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
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; GFX10-PACKED-NEXT: v_lshrrev_b32_e32 v0, 16, v1
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; GFX10-PACKED-NEXT: ; return to shader part epilog
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;
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; GFX11-PACKED-LABEL: tbuffer_load_d16_xyzw:
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; GFX11-PACKED: ; %bb.0: ; %main_body
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; GFX11-PACKED-NEXT: tbuffer_load_d16_format_xyzw v[0:1], off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
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; GFX11-PACKED-NEXT: s_waitcnt vmcnt(0)
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; GFX11-PACKED-NEXT: v_lshrrev_b32_e32 v0, 16, v1
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; GFX11-PACKED-NEXT: ; return to shader part epilog
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main_body:
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%data = call <4 x half> @llvm.amdgcn.raw.ptr.tbuffer.load.v4f16(ptr addrspace(8) %rsrc, i32 0, i32 0, i32 22, i32 0)
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%elt = extractelement <4 x half> %data, i32 3
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ret half %elt
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}
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declare half @llvm.amdgcn.raw.ptr.tbuffer.load.f16(ptr addrspace(8), i32, i32, i32, i32)
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declare <2 x half> @llvm.amdgcn.raw.ptr.tbuffer.load.v2f16(ptr addrspace(8), i32, i32, i32, i32)
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declare <3 x half> @llvm.amdgcn.raw.ptr.tbuffer.load.v3f16(ptr addrspace(8), i32, i32, i32, i32)
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declare <4 x half> @llvm.amdgcn.raw.ptr.tbuffer.load.v4f16(ptr addrspace(8), i32, i32, i32, i32)
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