9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
70 lines
2.8 KiB
LLVM
70 lines
2.8 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}const_load_no_shrink_dword_to_unaligned_byte:
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; GCN: s_load_dword s{{[0-9]+}}
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; GCN: s_load_dword [[LD:s[0-9]+]],
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; GCN: s_bfe_i32 s{{[0-9]+}}, [[LD]], 0x10013
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define amdgpu_kernel void @const_load_no_shrink_dword_to_unaligned_byte(ptr addrspace(1) %out, ptr addrspace(4) %in, i32 %x) {
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%ptr = getelementptr i32, ptr addrspace(4) %in, i32 %x
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%load = load i32, ptr addrspace(4) %ptr, align 4
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%and = and i32 %load, 524288
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%cmp = icmp eq i32 %and, 0
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%sel = select i1 %cmp, i32 0, i32 -1
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store i32 %sel, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: const_load_no_shrink_dword_to_aligned_byte:
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; GCN: s_load_dword s{{[0-9]+}}
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; GCN: s_load_dword [[LD:s[0-9]+]],
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; GCN: s_bfe_i32 s{{[0-9]+}}, [[LD]], 0x10003
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define amdgpu_kernel void @const_load_no_shrink_dword_to_aligned_byte(ptr addrspace(1) %out, ptr addrspace(4) %in, i32 %x) {
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%ptr = getelementptr i32, ptr addrspace(4) %in, i32 %x
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%load = load i32, ptr addrspace(4) %ptr, align 4
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%and = and i32 %load, 8
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%cmp = icmp eq i32 %and, 0
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%sel = select i1 %cmp, i32 0, i32 -1
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store i32 %sel, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: global_load_no_shrink_dword_to_unaligned_byte:
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; GCN: s_load_dword s{{[0-9]+}}
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; GCN: s_load_dword [[LD:s[0-9]+]],
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; GCN: s_bfe_i32 s{{[0-9]+}}, [[LD]], 0x10013
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define amdgpu_kernel void @global_load_no_shrink_dword_to_unaligned_byte(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in, i32 %x) {
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%ptr = getelementptr i32, ptr addrspace(1) %in, i32 %x
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%load = load i32, ptr addrspace(1) %ptr, align 4
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%and = and i32 %load, 524288
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%cmp = icmp eq i32 %and, 0
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%sel = select i1 %cmp, i32 0, i32 -1
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store i32 %sel, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: global_load_no_shrink_dword_to_aligned_byte:
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; GCN: s_load_dword s{{[0-9]+}}
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; GCN: s_load_dword [[LD:s[0-9]+]],
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; GCN: s_bfe_i32 s{{[0-9]+}}, [[LD]], 0x10003
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define amdgpu_kernel void @global_load_no_shrink_dword_to_aligned_byte(ptr addrspace(1) %out, ptr addrspace(1) %in, i32 %x) {
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%ptr = getelementptr i32, ptr addrspace(1) %in, i32 %x
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%load = load i32, ptr addrspace(1) %ptr, align 4
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%and = and i32 %load, 8
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%cmp = icmp eq i32 %and, 0
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%sel = select i1 %cmp, i32 0, i32 -1
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store i32 %sel, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: const_load_shrink_dword_to_unaligned_byte:
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; GCN: global_load_ushort
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define amdgpu_kernel void @const_load_shrink_dword_to_unaligned_byte(ptr addrspace(1) %out, ptr addrspace(4) %in, i32 %x) {
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%ptr = getelementptr i32, ptr addrspace(4) %in, i32 %x
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%load = load i32, ptr addrspace(4) %ptr, align 2
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%and = and i32 %load, 524288
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%cmp = icmp eq i32 %and, 0
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%sel = select i1 %cmp, i32 0, i32 -1
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store i32 %sel, ptr addrspace(1) %out
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ret void
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}
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