a1710eb3cd
The LIT test cases were migrated with the script provided by Nikita Popov. No manual changes were made. Committed without review since no functional changes, after consultation with uweigand.
171 lines
4.5 KiB
LLVM
171 lines
4.5 KiB
LLVM
; Test load-and-trap instructions (LLGFAT/LLGFTAT)
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s
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declare void @llvm.trap()
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; Check LLGFAT with no displacement.
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define i64 @f1(ptr %ptr) {
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; CHECK-LABEL: f1:
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; CHECK: llgfat %r2, 0(%r2)
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; CHECK: br %r14
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entry:
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%val = load i32, ptr %ptr
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%ext = zext i32 %val to i64
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%cmp = icmp eq i64 %ext, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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if.end: ; preds = %entry
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ret i64 %ext
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}
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; Check the high end of the LLGFAT range.
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define i64 @f2(ptr %src) {
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; CHECK-LABEL: f2:
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; CHECK: llgfat %r2, 524284(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32, ptr %src, i64 131071
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%val = load i32, ptr %ptr
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%ext = zext i32 %val to i64
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%cmp = icmp eq i64 %ext, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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if.end: ; preds = %entry
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ret i64 %ext
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f3(ptr %src) {
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; CHECK-LABEL: f3:
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; CHECK: agfi %r2, 524288
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; CHECK: llgfat %r2, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32, ptr %src, i64 131072
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%val = load i32, ptr %ptr
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%ext = zext i32 %val to i64
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%cmp = icmp eq i64 %ext, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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if.end: ; preds = %entry
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ret i64 %ext
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}
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; Check that LLGFAT allows an index.
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define i64 @f4(i64 %src, i64 %index) {
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; CHECK-LABEL: f4:
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; CHECK: llgfat %r2, 524287(%r3,%r2)
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524287
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%ptr = inttoptr i64 %add2 to ptr
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%val = load i32, ptr %ptr
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%ext = zext i32 %val to i64
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%cmp = icmp eq i64 %ext, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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if.end: ; preds = %entry
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ret i64 %ext
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}
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; Check LLGTAT with no displacement.
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define i64 @f5(ptr %ptr) {
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; CHECK-LABEL: f5:
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; CHECK: llgtat %r2, 0(%r2)
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; CHECK: br %r14
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entry:
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%val = load i32, ptr %ptr
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%ext = zext i32 %val to i64
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%and = and i64 %ext, 2147483647
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%cmp = icmp eq i64 %and, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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if.end: ; preds = %entry
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ret i64 %and
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}
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; Check the high end of the LLGTAT range.
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define i64 @f6(ptr %src) {
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; CHECK-LABEL: f6:
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; CHECK: llgtat %r2, 524284(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32, ptr %src, i64 131071
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%val = load i32, ptr %ptr
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%ext = zext i32 %val to i64
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%and = and i64 %ext, 2147483647
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%cmp = icmp eq i64 %and, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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if.end: ; preds = %entry
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ret i64 %and
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f7(ptr %src) {
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; CHECK-LABEL: f7:
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; CHECK: agfi %r2, 524288
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; CHECK: llgtat %r2, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32, ptr %src, i64 131072
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%val = load i32, ptr %ptr
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%ext = zext i32 %val to i64
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%and = and i64 %ext, 2147483647
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%cmp = icmp eq i64 %and, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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if.end: ; preds = %entry
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ret i64 %and
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}
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; Check that LLGTAT allows an index.
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define i64 @f8(i64 %src, i64 %index) {
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; CHECK-LABEL: f8:
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; CHECK: llgtat %r2, 524287(%r3,%r2)
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524287
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%ptr = inttoptr i64 %add2 to ptr
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%val = load i32, ptr %ptr
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%ext = zext i32 %val to i64
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%and = and i64 %ext, 2147483647
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%cmp = icmp eq i64 %and, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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if.end: ; preds = %entry
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ret i64 %and
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}
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