9375962ac9
The vast majority of the following (very common) opcodes were always called with identical arguments: - `GIM_CheckType` for the root - `GIM_CheckRegBankForClass` for the root - `GIR_Copy` between the old and new root - `GIR_ConstrainSelectedInstOperands` on the new root - `GIR_BuildMI` to create the new root I added overloaded version of each opcode specialized for the root instructions. It always saves between 1 and 2 bytes per instance depending on the number of arguments specialized into the opcode. Some of these opcodes had between 5 and 15k occurences in the AArch64 GlobalISel Match Table. Additionally, the following opcodes are almost always used in the same sequence: - `GIR_EraseFromParent 0` + `GIR_Done` - `GIR_EraseRootFromParent_Done` has been created to do both. Saves 2 bytes per occurence. - `GIR_IsSafeToFold` was *always* called for each InsnID except 0. - Changed the opcode to take the number of instructions to check after `MI[0]` The savings from these are pretty neat. For `AArch64GenGlobalISel.inc`: - `AArch64InstructionSelector.cpp.o` goes down from 772kb to 704kb (-10% code size) - Self-reported MatchTable size goes from 420380 bytes to 352426 bytes (~ -17%) A smaller match table means a faster match table because we spend less time iterating and decoding. I don't have a solid measurement methodology for GlobalISel performance so I don't have precise numbers but I saw a few % of improvements in a simple testcase.
88 lines
4.2 KiB
TableGen
88 lines
4.2 KiB
TableGen
// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
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include "llvm/Target/Target.td"
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def TestTargetInstrInfo : InstrInfo;
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def TestTarget : Target {
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let InstructionSet = TestTargetInstrInfo;
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}
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def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
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def SPECIAL : Register<"special"> { let Namespace = "MyTarget"; }
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def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
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def Special32 : RegisterClass<"MyTarget", [i32], 32, (add SPECIAL)>;
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class I<dag OOps, dag IOps, list<dag> Pat>
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: Instruction {
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let Namespace = "MyTarget";
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let OutOperandList = OOps;
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let InOperandList = IOps;
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let Pattern = Pat;
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}
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// Try a normal physical register use.
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// GISEL: GIM_Try,
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// GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
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// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ADD),
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// GISEL-NEXT: // MIs[0] DstI[dst]
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// GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
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// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
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// GISEL-NEXT: // MIs[0] src0
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// GISEL-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
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// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
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// GISEL-NEXT: // MIs[0] Operand 2
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// GISEL-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
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// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::Special32RegClassID),
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// GISEL-NEXT: // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src0, SPECIAL:{ *:[i32] }) => (ADD_PHYS:{ *:[i32] } GPR32:{ *:[i32] }:$src0)
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// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
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// GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(MyTarget::SPECIAL), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
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// GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // SPECIAL
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// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::ADD_PHYS),
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// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
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// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src0
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// GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
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// GISEL-NEXT: // GIR_Coverage, 0,
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// GISEL-NEXT: GIR_EraseRootFromParent_Done,
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def ADD_PHYS : I<(outs GPR32:$dst), (ins GPR32:$src0),
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[(set GPR32:$dst, (add GPR32:$src0, SPECIAL))]> {
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let Uses = [SPECIAL];
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}
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// Try using the name of the physreg in another operand.
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// GISEL: GIM_Try,
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// GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
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// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL),
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// GISEL-NEXT: // MIs[0] DstI[dst]
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// GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
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// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
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// GISEL-NEXT: // MIs[0] SPECIAL
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// GISEL-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
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// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
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// GISEL-NEXT: // MIs[0] Operand 2
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// GISEL-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
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// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::Special32RegClassID),
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// GISEL-NEXT: // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$SPECIAL, SPECIAL:{ *:[i32] }) => (MUL_PHYS:{ *:[i32] } GPR32:{ *:[i32] }:$SPECIAL)
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// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
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// GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(MyTarget::SPECIAL), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
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// GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // SPECIAL
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// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MUL_PHYS),
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// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
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// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // SPECIAL
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// GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
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// GISEL-NEXT: // GIR_Coverage, 1,
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// GISEL-NEXT: GIR_EraseRootFromParent_Done,
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def MUL_PHYS : I<(outs GPR32:$dst), (ins GPR32:$SPECIAL),
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[(set GPR32:$dst, (mul GPR32:$SPECIAL, SPECIAL))]> {
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let Uses = [SPECIAL];
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}
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// Try giving the physical operand a name
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// def ADD_PHYS : I<(outs GPR32:$dst), (ins GPR32:$src0),
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// [(set GPR32:$dst, (add GPR32:$src0, SPECIAL:$special))]> {
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// let Uses = [SPECIAL];
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// }
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