We want each register to have a canonical type, which means the best place to store this is in MachineRegisterInfo rather than on every MachineInstr that happens to use or define that register. Most changes following from this are pretty simple (you need an MRI anyway if you're going to be doing any transformations, so just check the type there). But legalization doesn't really want to check redundant operands (when, for example, a G_ADD only ever has one type) so I've made use of MCInstrDesc's operand type field to encode these constraints and limit legalization's work. As an added bonus, more validation is possible, both in MachineVerifier and MachineIRBuilder (coming soon). llvm-svn: 281035
182 lines
6.3 KiB
C++
182 lines
6.3 KiB
C++
//===-- llvm/CodeGen/GlobalISel/MachineLegalizePass.cpp -------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file implements the LegalizeHelper class to legalize individual
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/// instructions and the MachineLegalizePass wrapper pass for the primary
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/// legalization.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/MachineLegalizePass.h"
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#include "llvm/CodeGen/GlobalISel/MachineLegalizeHelper.h"
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#include "llvm/CodeGen/GlobalISel/MachineLegalizer.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#define DEBUG_TYPE "legalize-mir"
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using namespace llvm;
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char MachineLegalizePass::ID = 0;
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INITIALIZE_PASS_BEGIN(MachineLegalizePass, DEBUG_TYPE,
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"Legalize the Machine IR a function's Machine IR", false,
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false)
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INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
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INITIALIZE_PASS_END(MachineLegalizePass, DEBUG_TYPE,
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"Legalize the Machine IR a function's Machine IR", false,
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false)
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MachineLegalizePass::MachineLegalizePass() : MachineFunctionPass(ID) {
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initializeMachineLegalizePassPass(*PassRegistry::getPassRegistry());
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}
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void MachineLegalizePass::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<TargetPassConfig>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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void MachineLegalizePass::init(MachineFunction &MF) {
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}
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bool MachineLegalizePass::combineExtracts(MachineInstr &MI,
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MachineRegisterInfo &MRI,
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const TargetInstrInfo &TII) {
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bool Changed = false;
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if (MI.getOpcode() != TargetOpcode::G_EXTRACT)
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return Changed;
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unsigned NumDefs = (MI.getNumOperands() - 1) / 2;
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unsigned SrcReg = MI.getOperand(NumDefs).getReg();
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MachineInstr &SeqI = *MRI.def_instr_begin(SrcReg);
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if (SeqI.getOpcode() != TargetOpcode::G_SEQUENCE)
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return Changed;
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unsigned NumSeqSrcs = (SeqI.getNumOperands() - 1) / 2;
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bool AllDefsReplaced = true;
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// Try to match each register extracted with a corresponding insertion formed
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// by the G_SEQUENCE.
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for (unsigned Idx = 0, SeqIdx = 0; Idx < NumDefs; ++Idx) {
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MachineOperand &ExtractMO = MI.getOperand(Idx);
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assert(ExtractMO.isReg() && ExtractMO.isDef() &&
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"unexpected extract operand");
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unsigned ExtractReg = ExtractMO.getReg();
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unsigned ExtractPos = MI.getOperand(NumDefs + Idx + 1).getImm();
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while (SeqIdx < NumSeqSrcs &&
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SeqI.getOperand(2 * SeqIdx + 2).getImm() < ExtractPos)
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++SeqIdx;
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if (SeqIdx == NumSeqSrcs) {
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AllDefsReplaced = false;
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continue;
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}
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unsigned OrigReg = SeqI.getOperand(2 * SeqIdx + 1).getReg();
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if (SeqI.getOperand(2 * SeqIdx + 2).getImm() != ExtractPos ||
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MRI.getType(OrigReg) != MRI.getType(ExtractReg)) {
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AllDefsReplaced = false;
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continue;
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}
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assert(!TargetRegisterInfo::isPhysicalRegister(OrigReg) &&
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"unexpected physical register in G_SEQUENCE");
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// Finally we can replace the uses.
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for (auto &Use : MRI.use_operands(ExtractReg)) {
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Changed = true;
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Use.setReg(OrigReg);
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}
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}
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if (AllDefsReplaced) {
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// If SeqI was the next instruction in the BB and we removed it, we'd break
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// the outer iteration.
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assert(std::next(MachineBasicBlock::iterator(MI)) != SeqI &&
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"G_SEQUENCE does not dominate G_EXTRACT");
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MI.eraseFromParent();
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if (MRI.use_empty(SrcReg))
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SeqI.eraseFromParent();
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Changed = true;
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}
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return Changed;
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}
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bool MachineLegalizePass::runOnMachineFunction(MachineFunction &MF) {
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// If the ISel pipeline failed, do not bother running that pass.
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if (MF.getProperties().hasProperty(
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MachineFunctionProperties::Property::FailedISel))
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return false;
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DEBUG(dbgs() << "Legalize Machine IR for: " << MF.getName() << '\n');
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init(MF);
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const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
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const MachineLegalizer &Legalizer = *MF.getSubtarget().getMachineLegalizer();
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MachineLegalizeHelper Helper(MF);
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// FIXME: an instruction may need more than one pass before it is legal. For
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// example on most architectures <3 x i3> is doubly-illegal. It would
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// typically proceed along a path like: <3 x i3> -> <3 x i8> -> <8 x i8>. We
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// probably want a worklist of instructions rather than naive iterate until
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// convergence for performance reasons.
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bool Changed = false;
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MachineBasicBlock::iterator NextMI;
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for (auto &MBB : MF)
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for (auto MI = MBB.begin(); MI != MBB.end(); MI = NextMI) {
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// Get the next Instruction before we try to legalize, because there's a
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// good chance MI will be deleted.
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NextMI = std::next(MI);
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// Only legalize pre-isel generic instructions: others don't have types
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// and are assumed to be legal.
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if (!isPreISelGenericOpcode(MI->getOpcode()))
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continue;
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auto Res = Helper.legalizeInstr(*MI, Legalizer);
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// Error out if we couldn't legalize this instruction. We may want to fall
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// back to DAG ISel instead in the future.
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if (Res == MachineLegalizeHelper::UnableToLegalize) {
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if (!TPC.isGlobalISelAbortEnabled()) {
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MF.getProperties().set(
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MachineFunctionProperties::Property::FailedISel);
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return false;
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}
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std::string Msg;
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raw_string_ostream OS(Msg);
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OS << "unable to legalize instruction: ";
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MI->print(OS);
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report_fatal_error(OS.str());
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}
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Changed |= Res == MachineLegalizeHelper::Legalized;
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}
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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for (auto &MBB : MF) {
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for (auto MI = MBB.begin(); MI != MBB.end(); MI = NextMI) {
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// Get the next Instruction before we try to legalize, because there's a
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// good chance MI will be deleted.
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NextMI = std::next(MI);
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Changed |= combineExtracts(*MI, MRI, TII);
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}
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}
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return Changed;
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}
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