1eeb11bfd4
Summary:
Prevously assembler parsed all literals as either 32-bit integers or 32-bit floating-point values. Because of this we couldn't support f64 literals.
E.g. in instruction "v_fract_f64 v[0:1], 0.5", literal 0.5 was encoded as 32-bit literal 0x3f000000, which is incorrect and will be interpreted as 3.0517578125E-5 instead of 0.5. Correct encoding is inline constant 240 (optimal) or 32-bit literal 0x3FE00000 at least.
With this change the way immediate literals are parsed is changed. All literals are always parsed as 64-bit values either integer or floating-point. Then we convert parsed literals to correct form based on information about type of operand parsed (was literal floating or binary) and type of expected instruction operands (is this f32/64 or b32/64 instruction).
Here are rules how we convert literals:
- We parsed fp literal:
- Instruction expects 64-bit operand:
- If parsed literal is inlinable (e.g. v_fract_f64_e32 v[0:1], 0.5)
- then we do nothing this literal
- Else if literal is not-inlinable but instruction requires to inline it (e.g. this is e64 encoding, v_fract_f64_e64 v[0:1], 1.5)
- report error
- Else literal is not-inlinable but we can encode it as additional 32-bit literal constant
- If instruction expect fp operand type (f64)
- Check if low 32 bits of literal are zeroes (e.g. v_fract_f64 v[0:1], 1.5)
- If so then do nothing
- Else (e.g. v_fract_f64 v[0:1], 3.1415)
- report warning that low 32 bits will be set to zeroes and precision will be lost
- set low 32 bits of literal to zeroes
- Instruction expects integer operand type (e.g. s_mov_b64_e32 s[0:1], 1.5)
- report error as it is unclear how to encode this literal
- Instruction expects 32-bit operand:
- Convert parsed 64 bit fp literal to 32 bit fp. Allow lose of precision but not overflow or underflow
- Is this literal inlinable and are we required to inline literal (e.g. v_trunc_f32_e64 v0, 0.5)
- do nothing
- Else report error
- Do nothing. We can encode any other 32-bit fp literal (e.g. v_trunc_f32 v0, 10000000.0)
- Parsed binary literal:
- Is this literal inlinable (e.g. v_trunc_f32_e32 v0, 35)
- do nothing
- Else, are we required to inline this literal (e.g. v_trunc_f32_e64 v0, 35)
- report error
- Else, literal is not-inlinable and we are not required to inline it
- Are high 32 bit of literal zeroes or same as sign bit (32 bit)
- do nothing (e.g. v_trunc_f32 v0, 0xdeadbeef)
- Else
- report error (e.g. v_trunc_f32 v0, 0x123456789abcdef0)
For this change it is required that we know operand types of instruction (are they f32/64 or b32/64). I added several new register operands (they extend previous register operands) and set operand types to corresponding types:
'''
enum OperandType {
OPERAND_REG_IMM32_INT,
OPERAND_REG_IMM32_FP,
OPERAND_REG_INLINE_C_INT,
OPERAND_REG_INLINE_C_FP,
}
'''
This is not working yet:
- Several tests are failing
- Problems with predicate methods for inline immediates
- LLVM generated assembler parts try to select e64 encoding before e32.
More changes are required for several AsmOperands.
Reviewers: vpykhtin, tstellarAMD
Subscribers: arsenm, kzhuravl, artem.tamazov
Differential Revision: https://reviews.llvm.org/D22922
llvm-svn: 281050
106 lines
3.4 KiB
C++
106 lines
3.4 KiB
C++
//===-- AMDGPUBaseInfo.h - Top level definitions for AMDGPU -----*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
|
|
#define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
|
|
|
|
#include "AMDKernelCodeT.h"
|
|
#include "llvm/IR/CallingConv.h"
|
|
|
|
namespace llvm {
|
|
|
|
class FeatureBitset;
|
|
class Function;
|
|
class GlobalValue;
|
|
class MCContext;
|
|
class MCInstrDesc;
|
|
class MCRegisterInfo;
|
|
class MCSection;
|
|
class MCSubtargetInfo;
|
|
|
|
namespace AMDGPU {
|
|
|
|
struct IsaVersion {
|
|
unsigned Major;
|
|
unsigned Minor;
|
|
unsigned Stepping;
|
|
};
|
|
|
|
IsaVersion getIsaVersion(const FeatureBitset &Features);
|
|
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
|
|
const FeatureBitset &Features);
|
|
MCSection *getHSATextSection(MCContext &Ctx);
|
|
|
|
MCSection *getHSADataGlobalAgentSection(MCContext &Ctx);
|
|
|
|
MCSection *getHSADataGlobalProgramSection(MCContext &Ctx);
|
|
|
|
MCSection *getHSARodataReadonlyAgentSection(MCContext &Ctx);
|
|
|
|
bool isGroupSegment(const GlobalValue *GV);
|
|
bool isGlobalSegment(const GlobalValue *GV);
|
|
bool isReadOnlySegment(const GlobalValue *GV);
|
|
|
|
/// \returns Integer value requested using \p F's \p Name attribute.
|
|
///
|
|
/// \returns \p Default if attribute is not present.
|
|
///
|
|
/// \returns \p Default and emits error if requested value cannot be converted
|
|
/// to integer.
|
|
int getIntegerAttribute(const Function &F, StringRef Name, int Default);
|
|
|
|
/// \returns A pair of integer values requested using \p F's \p Name attribute
|
|
/// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
|
|
/// is false).
|
|
///
|
|
/// \returns \p Default if attribute is not present.
|
|
///
|
|
/// \returns \p Default and emits error if one of the requested values cannot be
|
|
/// converted to integer, or \p OnlyFirstRequired is false and "second" value is
|
|
/// not present.
|
|
std::pair<int, int> getIntegerPairAttribute(const Function &F,
|
|
StringRef Name,
|
|
std::pair<int, int> Default,
|
|
bool OnlyFirstRequired = false);
|
|
|
|
unsigned getInitialPSInputAddr(const Function &F);
|
|
|
|
bool isShader(CallingConv::ID cc);
|
|
bool isCompute(CallingConv::ID cc);
|
|
|
|
bool isSI(const MCSubtargetInfo &STI);
|
|
bool isCI(const MCSubtargetInfo &STI);
|
|
bool isVI(const MCSubtargetInfo &STI);
|
|
|
|
/// If \p Reg is a pseudo reg, return the correct hardware register given
|
|
/// \p STI otherwise return \p Reg.
|
|
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
|
|
|
|
/// \brief Can this operand also contain immediate values?
|
|
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
|
|
|
|
/// \brief Is this floating-point operand?
|
|
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
|
|
|
|
/// \brief Does this opearnd support only inlinable literals?
|
|
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
|
|
|
|
/// \brief Get size of register operand
|
|
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
|
|
unsigned OpNo);
|
|
|
|
/// \brief Is this literal inlinable
|
|
bool isInlinableLiteral64(int64_t Literal, bool IsVI);
|
|
bool isInlinableLiteral32(int32_t Literal, bool IsVI);
|
|
|
|
} // end namespace AMDGPU
|
|
} // end namespace llvm
|
|
|
|
#endif
|