I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line with a #include and let it re-sort things according to the precise LLVM rules for include ordering baked into clang-format these days. I've reverted a number of files where the results of sorting includes isn't healthy. Either places where we have legacy code relying on particular include ordering (where possible, I'll fix these separately) or where we have particular formatting around #include lines that I didn't want to disturb in this patch. This patch is *entirely* mechanical. If you get merge conflicts or anything, just ignore the changes in this patch and run clang-format over your #include lines in the files. Sorry for any noise here, but it is important to keep these things stable. I was seeing an increasing number of patches with irrelevant re-ordering of #include lines because clang-format was used. This patch at least isolates that churn, makes it easy to skip when resolving conflicts, and gets us to a clean baseline (again). llvm-svn: 304787
185 lines
6.6 KiB
C++
185 lines
6.6 KiB
C++
//===- Mips16FrameLowering.cpp - Mips16 Frame Information -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips16 implementation of TargetFrameLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "Mips16FrameLowering.h"
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#include "MCTargetDesc/MipsBaseInfo.h"
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#include "Mips16InstrInfo.h"
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#include "MipsInstrInfo.h"
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#include "MipsRegisterInfo.h"
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#include "MipsSubtarget.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/IR/DebugLoc.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDwarf.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MachineLocation.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include <cassert>
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#include <cstdint>
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#include <vector>
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using namespace llvm;
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Mips16FrameLowering::Mips16FrameLowering(const MipsSubtarget &STI)
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: MipsFrameLowering(STI, STI.stackAlignment()) {}
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void Mips16FrameLowering::emitPrologue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
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MachineFrameInfo &MFI = MF.getFrameInfo();
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const Mips16InstrInfo &TII =
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*static_cast<const Mips16InstrInfo *>(STI.getInstrInfo());
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MachineBasicBlock::iterator MBBI = MBB.begin();
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// Debug location must be unknown since the first debug location is used
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// to determine the end of the prologue.
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DebugLoc dl;
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uint64_t StackSize = MFI.getStackSize();
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// No need to allocate space on the stack.
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if (StackSize == 0 && !MFI.adjustsStack()) return;
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MachineModuleInfo &MMI = MF.getMMI();
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const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
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MachineLocation DstML, SrcML;
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// Adjust stack.
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TII.makeFrame(Mips::SP, StackSize, MBB, MBBI);
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// emit ".cfi_def_cfa_offset StackSize"
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unsigned CFIIndex = MF.addFrameInst(
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MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize));
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
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if (!CSI.empty()) {
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const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
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for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
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E = CSI.end(); I != E; ++I) {
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int64_t Offset = MFI.getObjectOffset(I->getFrameIdx());
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unsigned Reg = I->getReg();
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unsigned DReg = MRI->getDwarfRegNum(Reg, true);
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unsigned CFIIndex = MF.addFrameInst(
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MCCFIInstruction::createOffset(nullptr, DReg, Offset));
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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}
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}
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if (hasFP(MF))
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BuildMI(MBB, MBBI, dl, TII.get(Mips::MoveR3216), Mips::S0)
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.addReg(Mips::SP).setMIFlag(MachineInstr::FrameSetup);
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}
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void Mips16FrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
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MachineFrameInfo &MFI = MF.getFrameInfo();
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const Mips16InstrInfo &TII =
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*static_cast<const Mips16InstrInfo *>(STI.getInstrInfo());
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DebugLoc dl = MBBI->getDebugLoc();
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uint64_t StackSize = MFI.getStackSize();
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if (!StackSize)
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return;
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if (hasFP(MF))
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BuildMI(MBB, MBBI, dl, TII.get(Mips::Move32R16), Mips::SP)
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.addReg(Mips::S0);
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// Adjust stack.
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// assumes stacksize multiple of 8
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TII.restoreFrame(Mips::SP, StackSize, MBB, MBBI);
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}
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bool Mips16FrameLowering::
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spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const {
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MachineFunction *MF = MBB.getParent();
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MachineBasicBlock *EntryBlock = &MF->front();
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//
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// Registers RA, S0,S1 are the callee saved registers and they
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// will be saved with the "save" instruction
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// during emitPrologue
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//
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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// Add the callee-saved register as live-in. Do not add if the register is
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// RA and return address is taken, because it has already been added in
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// method MipsTargetLowering::lowerRETURNADDR.
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// It's killed at the spill, unless the register is RA and return address
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// is taken.
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unsigned Reg = CSI[i].getReg();
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bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA)
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&& MF->getFrameInfo().isReturnAddressTaken();
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if (!IsRAAndRetAddrIsTaken)
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EntryBlock->addLiveIn(Reg);
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}
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return true;
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}
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bool Mips16FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const {
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//
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// Registers RA,S0,S1 are the callee saved registers and they will be restored
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// with the restore instruction during emitEpilogue.
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// We need to override this virtual function, otherwise llvm will try and
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// restore the registers on it's on from the stack.
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//
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return true;
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}
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bool
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Mips16FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
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const MachineFrameInfo &MFI = MF.getFrameInfo();
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// Reserve call frame if the size of the maximum call frame fits into 15-bit
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// immediate field and there are no variable sized objects on the stack.
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return isInt<15>(MFI.getMaxCallFrameSize()) && !MFI.hasVarSizedObjects();
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}
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void Mips16FrameLowering::determineCalleeSaves(MachineFunction &MF,
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BitVector &SavedRegs,
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RegScavenger *RS) const {
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TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
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const Mips16InstrInfo &TII =
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*static_cast<const Mips16InstrInfo *>(STI.getInstrInfo());
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const MipsRegisterInfo &RI = TII.getRegisterInfo();
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const BitVector Reserved = RI.getReservedRegs(MF);
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bool SaveS2 = Reserved[Mips::S2];
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if (SaveS2)
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SavedRegs.set(Mips::S2);
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if (hasFP(MF))
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SavedRegs.set(Mips::S0);
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}
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const MipsFrameLowering *
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llvm::createMips16FrameLowering(const MipsSubtarget &ST) {
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return new Mips16FrameLowering(ST);
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}
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