d6a36ae282
This adds a callback to the LLVMTargetMachine that lets target indicate that they do not pass the machine verifier checks in all cases yet. This is intended to be a temporary measure while the targets are fixed allowing us to enable the machine verifier by default with EXPENSIVE_CHECKS enabled! Differential Revision: https://reviews.llvm.org/D33696 llvm-svn: 304320
102 lines
3.0 KiB
C++
102 lines
3.0 KiB
C++
//===- MipsTargetMachine.h - Define TargetMachine for Mips ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the Mips specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_MIPS_MIPSTARGETMACHINE_H
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#define LLVM_LIB_TARGET_MIPS_MIPSTARGETMACHINE_H
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#include "MCTargetDesc/MipsABIInfo.h"
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#include "MipsSubtarget.h"
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#include "llvm/ADT/Optional.h"
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#include "llvm/ADT/StringMap.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Support/CodeGen.h"
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#include "llvm/Target/TargetMachine.h"
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#include <memory>
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namespace llvm {
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class MipsTargetMachine : public LLVMTargetMachine {
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bool isLittle;
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std::unique_ptr<TargetLoweringObjectFile> TLOF;
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// Selected ABI
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MipsABIInfo ABI;
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MipsSubtarget *Subtarget;
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MipsSubtarget DefaultSubtarget;
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MipsSubtarget NoMips16Subtarget;
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MipsSubtarget Mips16Subtarget;
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mutable StringMap<std::unique_ptr<MipsSubtarget>> SubtargetMap;
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public:
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MipsTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Optional<Reloc::Model> RM, CodeModel::Model CM,
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CodeGenOpt::Level OL, bool isLittle);
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~MipsTargetMachine() override;
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TargetIRAnalysis getTargetIRAnalysis() override;
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const MipsSubtarget *getSubtargetImpl() const {
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if (Subtarget)
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return Subtarget;
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return &DefaultSubtarget;
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}
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const MipsSubtarget *getSubtargetImpl(const Function &F) const override;
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/// \brief Reset the subtarget for the Mips target.
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void resetSubtarget(MachineFunction *MF);
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// Pass Pipeline Configuration
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TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
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TargetLoweringObjectFile *getObjFileLowering() const override {
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return TLOF.get();
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}
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bool isLittleEndian() const { return isLittle; }
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const MipsABIInfo &getABI() const { return ABI; }
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bool isMachineVerifierClean() const override {
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return false;
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}
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};
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/// Mips32/64 big endian target machine.
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///
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class MipsebTargetMachine : public MipsTargetMachine {
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virtual void anchor();
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public:
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MipsebTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Optional<Reloc::Model> RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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/// Mips32/64 little endian target machine.
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///
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class MipselTargetMachine : public MipsTargetMachine {
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virtual void anchor();
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public:
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MipselTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Optional<Reloc::Model> RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_MIPS_MIPSTARGETMACHINE_H
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