537d039104
Re-apply r276044/r279124/r305516. Fixed a problem where we would refuse to place spills as the very first instruciton of a basic block and thus artifically increase pressure (test in test/CodeGen/PowerPC/scavenging.mir:spill_at_begin) This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 llvm-svn: 305625
47 lines
1.9 KiB
LLVM
47 lines
1.9 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7m -arm-execute-only -O0 %s -o - \
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; RUN: | FileCheck --check-prefix=CHECK-SUBW-ADDW %s
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; RUN: llc < %s -mtriple=thumbv8m.base -arm-execute-only -O0 %s -o - \
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; RUN: | FileCheck --check-prefix=CHECK-MOVW-MOVT-ADD %s
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; RUN: llc < %s -mtriple=thumbv8m.main -arm-execute-only -O0 %s -o - \
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; RUN: | FileCheck --check-prefix=CHECK-SUBW-ADDW %s
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define i8 @test_big_stack_frame() {
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; CHECK-SUBW-ADDW-LABEL: test_big_stack_frame:
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; CHECK-SUBW-ADDW-NOT: ldr {{r[0-9]+}}, .{{.*}}
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; CHECK-SUBW-ADDW: sub.w sp, sp, #65536
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; CHECK-SUBW-ADDW-NOT: ldr {{r[0-9]+}}, .{{.*}}
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; CHECK-SUBW-ADDW: add.w [[REG1:r[0-9]+|lr]], sp, #255
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; CHECK-SUBW-ADDW: add.w {{r[0-9]+}}, [[REG1]], #65280
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; CHECK-SUBW-ADDW-NOT: ldr {{r[0-9]+}}, .{{.*}}
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; CHECK-SUBW-ADDW: add.w [[REGX:r[0-9]+|lr]], sp, #61440
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; CHECK-SUBW-ADDW-NOT: ldr {{r[0-9]+}}, .{{.*}}
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; CHECK-SUBW-ADDW: add.w sp, sp, #65536
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; CHECK-MOVW-MOVT-ADD-LABEL: test_big_stack_frame:
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; CHECK-MOVW-MOVT-ADD-NOT: ldr {{r[0-9]+}}, .{{.*}}
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; CHECK-MOVW-MOVT-ADD: movw [[REG1:r[0-9]+]], #0
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; CHECK-MOVW-MOVT-ADD: movt [[REG1]], #65535
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; CHECK-MOVW-MOVT-ADD: add sp, [[REG1]]
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; CHECK-MOVW-MOVT-ADD-NOT: ldr {{r[0-9]+}}, .{{.*}}
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; CHECK-MOVW-MOVT-ADD: movw [[REG2:r[0-9]+]], #65532
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; CHECK-MOVW-MOVT-ADD: movt [[REG2]], #0
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; CHECK-MOVW-MOVT-ADD: add [[REG2]], sp
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; CHECK-MOVW-MOVT-ADD-NOT: ldr {{r[0-9]+}}, .{{.*}}
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; CHECK-MOVW-MOVT-ADD: movw [[REG3:r[0-9]+]], #65532
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; CHECK-MOVW-MOVT-ADD: movt [[REG3]], #0
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; CHECK-MOVW-MOVT-ADD: add [[REG3]], sp
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; CHECK-MOVW-MOVT-ADD-NOT: ldr {{r[0-9]+}}, .{{.*}}
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; CHECK-MOVW-MOVT-ADD: movw [[REG4:r[0-9]+]], #0
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; CHECK-MOVW-MOVT-ADD: movt [[REG4]], #1
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; CHECK-MOVW-MOVT-ADD: add sp, [[REG4]]
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entry:
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%s1 = alloca i8
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%buffer = alloca [65528 x i8], align 1
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call void @foo(i8* %s1)
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%load = load i8, i8* %s1
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ret i8 %load
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}
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declare void @foo(i8*)
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