537d039104
Re-apply r276044/r279124/r305516. Fixed a problem where we would refuse to place spills as the very first instruciton of a basic block and thus artifically increase pressure (test in test/CodeGen/PowerPC/scavenging.mir:spill_at_begin) This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 llvm-svn: 305625
97 lines
2.3 KiB
YAML
97 lines
2.3 KiB
YAML
# RUN: llc -o - %s -mtriple=thumbv7-- -run-pass=stack-protector -run-pass=prologepilog | FileCheck %s
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---
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# This should trigger an emergency spill in the register scavenger because the
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# frame offset into the large argument is too large.
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# CHECK-LABEL: name: func0
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# CHECK: t2STRi12 killed [[SPILLED:%r[0-9]+]], %sp, 0, 14, _ :: (store 4 into %stack.0)
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# CHECK: [[SPILLED]] = t2ADDri killed %sp, 4096, 14, _, _
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# CHECK: %sp = t2LDRi12 killed [[SPILLED]], 40, 14, _ :: (load 4)
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# CHECK: [[SPILLED]] = t2LDRi12 %sp, 0, 14, _ :: (load 4 from %stack.0)
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name: func0
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tracksRegLiveness: true
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fixedStack:
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- { id: 0, offset: 4084, size: 4, alignment: 4, isImmutable: true,
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isAliased: false }
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- { id: 1, offset: -12, size: 4096, alignment: 4, isImmutable: false,
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isAliased: false }
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body: |
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bb.0:
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%r0 = IMPLICIT_DEF
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%r1 = IMPLICIT_DEF
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%r2 = IMPLICIT_DEF
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%r3 = IMPLICIT_DEF
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%r4 = IMPLICIT_DEF
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%r5 = IMPLICIT_DEF
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%r6 = IMPLICIT_DEF
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%r7 = IMPLICIT_DEF
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%r8 = IMPLICIT_DEF
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%r9 = IMPLICIT_DEF
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%r10 = IMPLICIT_DEF
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%r11 = IMPLICIT_DEF
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%r12 = IMPLICIT_DEF
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%lr = IMPLICIT_DEF
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%sp = t2LDRi12 %fixed-stack.0, 0, 14, _ :: (load 4)
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KILL %r0
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KILL %r1
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KILL %r2
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KILL %r3
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KILL %r4
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KILL %r5
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KILL %r6
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KILL %r7
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KILL %r8
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KILL %r9
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KILL %r10
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KILL %r11
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KILL %r12
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KILL %lr
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...
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---
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# This should not trigger an emergency spill yet.
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# CHECK-LABEL: name: func1
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# CHECK-NOT: t2STRi12
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# CHECK-NOT: t2ADDri
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# CHECK: %r11 = t2LDRi12 %sp, 4092, 14, _ :: (load 4)
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# CHECK-NOT: t2LDRi12
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name: func1
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tracksRegLiveness: true
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fixedStack:
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- { id: 0, offset: 4044, size: 4, alignment: 4, isImmutable: true,
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isAliased: false }
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- { id: 1, offset: -12, size: 4056, alignment: 4, isImmutable: false,
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isAliased: false }
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body: |
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bb.0:
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%r0 = IMPLICIT_DEF
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%r1 = IMPLICIT_DEF
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%r2 = IMPLICIT_DEF
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%r3 = IMPLICIT_DEF
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%r4 = IMPLICIT_DEF
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%r5 = IMPLICIT_DEF
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%r6 = IMPLICIT_DEF
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%r8 = IMPLICIT_DEF
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%r9 = IMPLICIT_DEF
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%r10 = IMPLICIT_DEF
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%r11 = IMPLICIT_DEF
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%r12 = IMPLICIT_DEF
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%lr = IMPLICIT_DEF
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%r11 = t2LDRi12 %fixed-stack.0, 0, 14, _ :: (load 4)
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KILL %r0
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KILL %r1
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KILL %r2
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KILL %r3
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KILL %r4
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KILL %r5
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KILL %r6
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KILL %r8
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KILL %r9
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KILL %r10
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KILL %r11
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KILL %r12
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KILL %lr
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...
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