95f24dca98
When SelectionDAG expands memcpy (or memmove) call into a sequence of load and store instructions, it disregards dereferenceable flag even the source pointer is known to be dereferenceable. This results in an assertion failure if SelectionDAG commonizes a load instruction generated for memcpy with another load instruction for the source pointer. This patch makes SelectionDAG to set the dereferenceable flag for the load instructions properly to avoid the assertion failure. Differential Revision: https://reviews.llvm.org/D34467 llvm-svn: 306209
75 lines
2.8 KiB
LLVM
75 lines
2.8 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
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; This code causes an assertion failure if dereferenceable flag is not properly set in the load generated for memcpy
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; CHECK-LABEL: @func
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; CHECK: lxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
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; CHECK-NOT: lxvd2x
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; CHECK: stxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
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; CHECK: stxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
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; CHECK: blr
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define void @func(i1 %flag) {
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entry:
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%pairs = alloca [4 x <2 x i64>], align 8
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%pair1 = getelementptr inbounds [4 x <2 x i64>], [4 x <2 x i64>]* %pairs, i64 0, i64 1
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%pair2 = getelementptr inbounds [4 x <2 x i64>], [4 x <2 x i64>]* %pairs, i64 0, i64 2
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%pvec1 = bitcast <2 x i64>* %pair1 to <2 x i64>*
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%pvec2 = bitcast <2 x i64>* %pair2 to <2 x i64>*
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%dst = bitcast [4 x <2 x i64>]* %pairs to i8*
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%src = bitcast <2 x i64>* %pair2 to i8*
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br i1 %flag, label %end, label %dummy
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end:
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; copy third element into first element by memcpy
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull %dst, i8* %src, i64 16, i32 8, i1 false)
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; copy third element into second element by LD/ST
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%vec2 = load <2 x i64>, <2 x i64>* %pvec2, align 8
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store <2 x i64> %vec2, <2 x i64>* %pvec1, align 8
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ret void
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dummy:
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; to make use of %src in another BB
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* %src, i8* %src, i64 0, i32 0, i1 false)
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br label %end
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}
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; CHECK-LABEL: @func2
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; CHECK: lxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
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; CHECK-NOT: lxvd2x
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; CHECK: stxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
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; CHECK: stxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
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; CHECK: blr
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define void @func2(i1 %flag) {
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entry:
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%pairs = alloca [4 x <2 x i64>], align 8
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%pair1 = getelementptr inbounds [4 x <2 x i64>], [4 x <2 x i64>]* %pairs, i64 0, i64 1
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%pair2 = getelementptr inbounds [4 x <2 x i64>], [4 x <2 x i64>]* %pairs, i64 0, i64 2
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%pvec1 = bitcast <2 x i64>* %pair1 to <2 x i64>*
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%pvec2 = bitcast <2 x i64>* %pair2 to <2 x i64>*
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%dst = bitcast [4 x <2 x i64>]* %pairs to i8*
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%src = bitcast <2 x i64>* %pair2 to i8*
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br i1 %flag, label %end, label %dummy
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end:
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; copy third element into first element by memcpy
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call void @llvm.memmove.p0i8.p0i8.i64(i8* nonnull %dst, i8* %src, i64 16, i32 8, i1 false)
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; copy third element into second element by LD/ST
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%vec2 = load <2 x i64>, <2 x i64>* %pvec2, align 8
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store <2 x i64> %vec2, <2 x i64>* %pvec1, align 8
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ret void
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dummy:
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; to make use of %src in another BB
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* %src, i8* %src, i64 0, i32 0, i1 false)
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br label %end
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}
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; Function Attrs: argmemonly nounwind
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32, i1) #1
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declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32, i1) #1
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attributes #1 = { argmemonly nounwind }
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