60fed1fef0
This pass performs peephole optimizations to cleanup ugly code sequences at MachineInstruction layer. Currently, the only optimization in this pass is to eliminate type promotion sequences for zero extending 32-bit subregisters to 64-bit registers. If the compiler could prove the zero extended source come from 32-bit subregistere then it is safe to erase those promotion sequece, because the upper half of the underlying 64-bit registers were zeroed implicitly already. Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 325991
109 lines
3.5 KiB
C++
109 lines
3.5 KiB
C++
//===-- BPFTargetMachine.cpp - Define TargetMachine for BPF ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Implements the info about BPF target spec.
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//
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//===----------------------------------------------------------------------===//
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#include "BPFTargetMachine.h"
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#include "BPF.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/LegacyPassManager.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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static cl::
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opt<bool> DisableMIPeephole("disable-bpf-peephole", cl::Hidden,
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cl::desc("Disable machine peepholes for BPF"));
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extern "C" void LLVMInitializeBPFTarget() {
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// Register the target.
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RegisterTargetMachine<BPFTargetMachine> X(getTheBPFleTarget());
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RegisterTargetMachine<BPFTargetMachine> Y(getTheBPFbeTarget());
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RegisterTargetMachine<BPFTargetMachine> Z(getTheBPFTarget());
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PassRegistry &PR = *PassRegistry::getPassRegistry();
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initializeBPFMIPeepholePass(PR);
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}
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// DataLayout: little or big endian
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static std::string computeDataLayout(const Triple &TT) {
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if (TT.getArch() == Triple::bpfeb)
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return "E-m:e-p:64:64-i64:64-n32:64-S128";
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else
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return "e-m:e-p:64:64-i64:64-n32:64-S128";
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}
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static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
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if (!RM.hasValue())
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return Reloc::PIC_;
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return *RM;
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}
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static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
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if (CM)
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return *CM;
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return CodeModel::Small;
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}
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BPFTargetMachine::BPFTargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Optional<Reloc::Model> RM,
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Optional<CodeModel::Model> CM,
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CodeGenOpt::Level OL, bool JIT)
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: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
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getEffectiveRelocModel(RM), getEffectiveCodeModel(CM),
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OL),
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TLOF(make_unique<TargetLoweringObjectFileELF>()),
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Subtarget(TT, CPU, FS, *this) {
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initAsmInfo();
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}
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namespace {
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// BPF Code Generator Pass Configuration Options.
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class BPFPassConfig : public TargetPassConfig {
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public:
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BPFPassConfig(BPFTargetMachine &TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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BPFTargetMachine &getBPFTargetMachine() const {
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return getTM<BPFTargetMachine>();
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}
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bool addInstSelector() override;
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void addMachineSSAOptimization() override;
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};
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}
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TargetPassConfig *BPFTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new BPFPassConfig(*this, PM);
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}
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// Install an instruction selector pass using
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// the ISelDag to gen BPF code.
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bool BPFPassConfig::addInstSelector() {
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addPass(createBPFISelDag(getBPFTargetMachine()));
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return false;
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}
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void BPFPassConfig::addMachineSSAOptimization() {
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// The default implementation must be called first as we want eBPF
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// Peephole ran at last.
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TargetPassConfig::addMachineSSAOptimization();
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const BPFSubtarget *Subtarget = getBPFTargetMachine().getSubtargetImpl();
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if (Subtarget->getHasAlu32() && !DisableMIPeephole)
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addPass(createBPFMIPeepholePass());
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}
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