48abac82b8
This reverts commit r323991. This commit breaks target that don't model all the register constraints in TableGen. So far the workaround was to set the hasExtraXXXRegAllocReq, but it proves that it doesn't cover all the cases. For instance, when mutating an instruction (like in the lowering of COPYs) the isRenamable flag is not properly updated. The same problem will happen when attaching machine operand from one instruction to another. Geoff Berry is working on a fix in https://reviews.llvm.org/D43042. llvm-svn: 325421
36 lines
937 B
LLVM
36 lines
937 B
LLVM
; RUN: llc -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 -verify-machineinstrs -o - %s | FileCheck %s
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; LLVM should be able to cope with multiple uses of the same flag-setting
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; instruction at different points of a routine. Either by rematerializing the
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; compare or by saving and restoring the flag register.
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declare void @bar()
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@var = global i32 0
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define i32 @test_multiflag(i32 %n, i32 %m, i32 %o) {
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; CHECK-LABEL: test_multiflag:
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%test = icmp ne i32 %n, %m
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; CHECK: cmp [[LHS:w[0-9]+]], [[RHS:w[0-9]+]]
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%val = zext i1 %test to i32
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; CHECK: cset {{[xw][0-9]+}}, ne
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store i32 %val, i32* @var
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call void @bar()
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; CHECK: bl bar
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; Currently, the comparison is emitted again. An MSR/MRS pair would also be
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; acceptable, but assuming the call preserves NZCV is not.
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br i1 %test, label %iftrue, label %iffalse
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; CHECK: cmp [[LHS]], [[RHS]]
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; CHECK: b.eq
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iftrue:
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ret i32 42
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iffalse:
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ret i32 0
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}
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