48abac82b8
This reverts commit r323991. This commit breaks target that don't model all the register constraints in TableGen. So far the workaround was to set the hasExtraXXXRegAllocReq, but it proves that it doesn't cover all the cases. For instance, when mutating an instruction (like in the lowering of COPYs) the isRenamable flag is not properly updated. The same problem will happen when attaching machine operand from one instruction to another. Geoff Berry is working on a fix in https://reviews.llvm.org/D43042. llvm-svn: 325421
116 lines
3.7 KiB
LLVM
116 lines
3.7 KiB
LLVM
; RUN: opt -S -mtriple=amdgcn-- -structurizecfg -si-annotate-control-flow < %s | FileCheck -check-prefix=OPT %s
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; OPT-LABEL: {{^}}define amdgpu_vs void @multi_else_break(
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; OPT: main_body:
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; OPT: LOOP.outer:
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; OPT: LOOP:
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; OPT: [[if:%[0-9]+]] = call { i1, i64 } @llvm.amdgcn.if(
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; OPT: [[if_exec:%[0-9]+]] = extractvalue { i1, i64 } [[if]], 1
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;
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; OPT: Flow:
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;
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; Ensure two else.break calls, for both the inner and outer loops
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; OPT: call i64 @llvm.amdgcn.else.break(i64 [[if_exec]],
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; OPT-NEXT: call i64 @llvm.amdgcn.else.break(i64 [[if_exec]],
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; OPT-NEXT: call void @llvm.amdgcn.end.cf
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;
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; OPT: Flow1:
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; GCN-LABEL: {{^}}multi_else_break:
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; GCN: [[OUTER_LOOP:BB[0-9]+_[0-9]+]]: ; %LOOP.outer{{$}}
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; GCN: [[INNER_LOOP:BB[0-9]+_[0-9]+]]: ; %LOOP{{$}}
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; GCN: s_and_saveexec_b64 [[SAVE_BREAK:s\[[0-9]+:[0-9]+\]]], vcc
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; GCN: BB{{[0-9]+}}_{{[0-9]+}}: ; %Flow{{$}}
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; GCN-NEXT: ; in Loop: Header=[[INNER_LOOP]] Depth=2
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; Ensure extra or eliminated
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; GCN-NEXT: s_or_b64 exec, exec, [[SAVE_BREAK]]
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; GCN-NEXT: s_or_b64 [[OR_BREAK:s\[[0-9]+:[0-9]+\]]], [[SAVE_BREAK]], s{{\[[0-9]+:[0-9]+\]}}
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; GCN-NEXT: s_andn2_b64 exec, exec, [[OR_BREAK]]
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; GCN-NEXT: s_cbranch_execnz [[INNER_LOOP]]
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; GCN: ; %bb.{{[0-9]+}}: ; %Flow1{{$}}
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; GCN-NEXT: ; in Loop: Header=[[OUTER_LOOP]] Depth=1
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; Ensure copy is eliminated
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; GCN-NEXT: s_or_b64 exec, exec, [[OR_BREAK]]
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; GCN-NEXT: s_or_b64 [[OUTER_OR_BREAK:s\[[0-9]+:[0-9]+\]]], [[SAVE_BREAK]], s{{\[[0-9]+:[0-9]+\]}}
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; GCN-NEXT: s_andn2_b64 exec, exec, [[OUTER_OR_BREAK]]
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; GCN-NEXT: s_cbranch_execnz [[OUTER_LOOP]]
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define amdgpu_vs void @multi_else_break(<4 x float> %vec, i32 %ub, i32 %cont) {
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main_body:
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br label %LOOP.outer
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LOOP.outer: ; preds = %ENDIF, %main_body
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%tmp43 = phi i32 [ 0, %main_body ], [ %tmp47, %ENDIF ]
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br label %LOOP
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LOOP: ; preds = %ENDIF, %LOOP.outer
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%tmp45 = phi i32 [ %tmp43, %LOOP.outer ], [ %tmp47, %ENDIF ]
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%tmp47 = add i32 %tmp45, 1
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%tmp48 = icmp slt i32 %tmp45, %ub
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br i1 %tmp48, label %ENDIF, label %IF
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IF: ; preds = %LOOP
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ret void
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ENDIF: ; preds = %LOOP
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%tmp51 = icmp eq i32 %tmp47, %cont
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br i1 %tmp51, label %LOOP, label %LOOP.outer
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}
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; OPT-LABEL: define amdgpu_kernel void @multi_if_break_loop(
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; OPT: llvm.amdgcn.break
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; OPT: llvm.amdgcn.loop
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; OPT: llvm.amdgcn.if.break
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; OPT: llvm.amdgcn.if.break
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; OPT: llvm.amdgcn.end.cf
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; GCN-LABEL: {{^}}multi_if_break_loop:
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; GCN: s_mov_b64 [[BREAK_REG:s\[[0-9]+:[0-9]+\]]], 0{{$}}
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; GCN: [[LOOP:BB[0-9]+_[0-9]+]]: ; %bb1{{$}}
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; Uses a copy intsead of an or
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; GCN: s_mov_b64 [[COPY:s\[[0-9]+:[0-9]+\]]], [[BREAK_REG]]
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; GCN: s_or_b64 [[BREAK_REG]], exec, [[COPY]]
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define amdgpu_kernel void @multi_if_break_loop(i32 %arg) #0 {
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bb:
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%tmp = sub i32 %id, %arg
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br label %bb1
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bb1:
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%lsr.iv = phi i32 [ undef, %bb ], [ %lsr.iv.next, %case0 ], [ %lsr.iv.next, %case1 ]
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%lsr.iv.next = add i32 %lsr.iv, 1
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%cmp0 = icmp slt i32 %lsr.iv.next, 0
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%load0 = load volatile i32, i32 addrspace(1)* undef, align 4
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switch i32 %load0, label %bb9 [
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i32 0, label %case0
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i32 1, label %case1
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]
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case0:
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%load1 = load volatile i32, i32 addrspace(1)* undef, align 4
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%cmp1 = icmp slt i32 %tmp, %load1
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br i1 %cmp1, label %bb1, label %bb9
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case1:
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%load2 = load volatile i32, i32 addrspace(1)* undef, align 4
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%cmp2 = icmp slt i32 %tmp, %load2
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br i1 %cmp2, label %bb1, label %bb9
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bb9:
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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