48abac82b8
This reverts commit r323991. This commit breaks target that don't model all the register constraints in TableGen. So far the workaround was to set the hasExtraXXXRegAllocReq, but it proves that it doesn't cover all the cases. For instance, when mutating an instruction (like in the lowering of COPYs) the isRenamable flag is not properly updated. The same problem will happen when attaching machine operand from one instruction to another. Geoff Berry is working on a fix in https://reviews.llvm.org/D43042. llvm-svn: 325421
88 lines
2.8 KiB
LLVM
88 lines
2.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=X32
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=X64
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define <2 x i64> @shl1(<4 x i32> %r, <4 x i32> %a) nounwind readnone ssp {
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; X32-LABEL: shl1:
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; X32: # %bb.0: # %entry
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; X32-NEXT: pslld $23, %xmm1
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; X32-NEXT: paddd {{\.LCPI.*}}, %xmm1
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; X32-NEXT: cvttps2dq %xmm1, %xmm1
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; X32-NEXT: pmulld %xmm1, %xmm0
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; X32-NEXT: retl
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;
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; X64-LABEL: shl1:
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; X64: # %bb.0: # %entry
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; X64-NEXT: pslld $23, %xmm1
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; X64-NEXT: paddd {{.*}}(%rip), %xmm1
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; X64-NEXT: cvttps2dq %xmm1, %xmm1
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; X64-NEXT: pmulld %xmm1, %xmm0
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; X64-NEXT: retq
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entry:
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; CHECK-NOT: shll
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; CHECK: pslld
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; CHECK: paddd
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; CHECK: cvttps2dq
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; CHECK: pmulld
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%shl = shl <4 x i32> %r, %a ; <<4 x i32>> [#uses=1]
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%tmp2 = bitcast <4 x i32> %shl to <2 x i64> ; <<2 x i64>> [#uses=1]
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ret <2 x i64> %tmp2
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}
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define <2 x i64> @shl2(<16 x i8> %r, <16 x i8> %a) nounwind readnone ssp {
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; X32-LABEL: shl2:
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; X32: # %bb.0: # %entry
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; X32-NEXT: movdqa %xmm0, %xmm2
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; X32-NEXT: psllw $5, %xmm1
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; X32-NEXT: movdqa %xmm2, %xmm3
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; X32-NEXT: psllw $4, %xmm3
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; X32-NEXT: pand {{\.LCPI.*}}, %xmm3
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; X32-NEXT: movdqa %xmm1, %xmm0
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; X32-NEXT: pblendvb %xmm0, %xmm3, %xmm2
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; X32-NEXT: movdqa %xmm2, %xmm3
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; X32-NEXT: psllw $2, %xmm3
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; X32-NEXT: pand {{\.LCPI.*}}, %xmm3
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; X32-NEXT: paddb %xmm1, %xmm1
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; X32-NEXT: movdqa %xmm1, %xmm0
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; X32-NEXT: pblendvb %xmm0, %xmm3, %xmm2
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; X32-NEXT: movdqa %xmm2, %xmm3
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; X32-NEXT: paddb %xmm3, %xmm3
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; X32-NEXT: paddb %xmm1, %xmm1
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; X32-NEXT: movdqa %xmm1, %xmm0
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; X32-NEXT: pblendvb %xmm0, %xmm3, %xmm2
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; X32-NEXT: movdqa %xmm2, %xmm0
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; X32-NEXT: retl
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;
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; X64-LABEL: shl2:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movdqa %xmm0, %xmm2
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; X64-NEXT: psllw $5, %xmm1
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; X64-NEXT: movdqa %xmm2, %xmm3
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; X64-NEXT: psllw $4, %xmm3
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; X64-NEXT: pand {{.*}}(%rip), %xmm3
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; X64-NEXT: movdqa %xmm1, %xmm0
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; X64-NEXT: pblendvb %xmm0, %xmm3, %xmm2
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; X64-NEXT: movdqa %xmm2, %xmm3
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; X64-NEXT: psllw $2, %xmm3
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; X64-NEXT: pand {{.*}}(%rip), %xmm3
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; X64-NEXT: paddb %xmm1, %xmm1
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; X64-NEXT: movdqa %xmm1, %xmm0
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; X64-NEXT: pblendvb %xmm0, %xmm3, %xmm2
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; X64-NEXT: movdqa %xmm2, %xmm3
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; X64-NEXT: paddb %xmm3, %xmm3
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; X64-NEXT: paddb %xmm1, %xmm1
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; X64-NEXT: movdqa %xmm1, %xmm0
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; X64-NEXT: pblendvb %xmm0, %xmm3, %xmm2
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; X64-NEXT: movdqa %xmm2, %xmm0
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; X64-NEXT: retq
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entry:
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; CHECK-NOT: shlb
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; CHECK: pblendvb
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; CHECK: pblendvb
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; CHECK: pblendvb
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%shl = shl <16 x i8> %r, %a ; <<16 x i8>> [#uses=1]
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%tmp2 = bitcast <16 x i8> %shl to <2 x i64> ; <<2 x i64>> [#uses=1]
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ret <2 x i64> %tmp2
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}
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