110 lines
3.4 KiB
C++
110 lines
3.4 KiB
C++
//===-- llvm/CodeGen/GlobalISel/IRTranslator.cpp - IRTranslator --*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the IRTranslator class.
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Constant.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Type.h"
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#include "llvm/IR/Value.h"
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#define DEBUG_TYPE "irtranslator"
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using namespace llvm;
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char IRTranslator::ID = 0;
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const VRegsSequence &IRTranslator::getOrCreateVRegs(const Value *Val) {
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VRegsSequence &ValRegSequence = ValToVRegs[Val];
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// Check if this is the first time we see Val.
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if (ValRegSequence.empty()) {
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// Fill ValRegsSequence with the sequence of registers
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// we need to concat together to produce the value.
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assert(Val->getType()->isSized() &&
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"Don't know how to create an empty vreg");
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assert(!Val->getType()->isAggregateType() && "Not yet implemented");
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unsigned Size = Val->getType()->getPrimitiveSizeInBits();
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unsigned VReg = MRI->createGenericVirtualRegister(Size);
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ValRegSequence.push_back(VReg);
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assert(isa<Constant>(Val) && "Not yet implemented");
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}
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assert(ValRegSequence.size() == 1 &&
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"We support only one vreg per value at the moment");
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return ValRegSequence;
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}
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MachineBasicBlock &IRTranslator::getOrCreateBB(const BasicBlock *BB) {
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MachineBasicBlock *&MBB = BBToMBB[BB];
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if (!MBB) {
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MachineFunction &MF = MIRBuilder->getMF();
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MBB = MF.CreateMachineBasicBlock();
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MF.push_back(MBB);
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}
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return *MBB;
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}
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bool IRTranslator::translateADD(const Instruction &Inst) {
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// Get or create a virtual register for each value.
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// Unless the value is a Constant => loadimm cst?
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// or inline constant each time?
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// Creation of a virtual register needs to have a size.
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unsigned Op0 = *getOrCreateVRegs(Inst.getOperand(0)).begin();
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unsigned Op1 = *getOrCreateVRegs(Inst.getOperand(1)).begin();
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unsigned Res = *getOrCreateVRegs(&Inst).begin();
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MIRBuilder->buildInstr(TargetOpcode::G_ADD, Res, Op0, Op1);
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return true;
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}
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bool IRTranslator::translate(const Instruction &Inst) {
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MIRBuilder->setDebugLoc(Inst.getDebugLoc());
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switch(Inst.getOpcode()) {
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case Instruction::Add: {
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return translateADD(Inst);
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default:
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llvm_unreachable("Opcode not supported");
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}
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}
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}
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void IRTranslator::finalize() {
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// Release the memory used by the different maps we
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// needed during the translation.
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ValToVRegs.clear();
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Constants.clear();
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}
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IRTranslator::IRTranslator()
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: MachineFunctionPass(ID) {
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}
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bool IRTranslator::runOnMachineFunction(MachineFunction &MF) {
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const Function &F = *MF.getFunction();
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MIRBuilder->setFunction(MF);
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MRI = &MF.getRegInfo();
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for (const BasicBlock &BB: F) {
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MachineBasicBlock &MBB = getOrCreateBB(&BB);
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MIRBuilder->setBasicBlock(MBB);
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for (const Instruction &Inst: BB) {
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bool Succeeded = translate(Inst);
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if (!Succeeded) {
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DEBUG(dbgs() << "Cannot translate: " << Inst << '\n');
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report_fatal_error("Unable to translate instruction");
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}
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}
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}
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return false;
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}
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