193259cbce
Not needed now that we require python 3. Reviewed By: kastiglione, JDevlieghere Differential Revision: https://reviews.llvm.org/D131761
100 lines
3.9 KiB
Python
100 lines
3.9 KiB
Python
"""
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Test the iteration protocol for frame registers.
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"""
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import lldb
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from lldbsuite.test.decorators import *
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from lldbsuite.test.lldbtest import *
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from lldbsuite.test import lldbutil
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class RegistersIteratorTestCase(TestBase):
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def setUp(self):
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# Call super's setUp().
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TestBase.setUp(self)
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# Find the line number to break inside main().
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self.line1 = line_number(
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'main.cpp', '// Set break point at this line.')
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def test_iter_registers(self):
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"""Test iterator works correctly for lldbutil.iter_registers()."""
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self.build()
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exe = self.getBuildArtifact("a.out")
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target = self.dbg.CreateTarget(exe)
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self.assertTrue(target, VALID_TARGET)
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breakpoint = target.BreakpointCreateByLocation("main.cpp", self.line1)
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self.assertTrue(breakpoint, VALID_BREAKPOINT)
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# Now launch the process, and do not stop at entry point.
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process = target.LaunchSimple(
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None, None, self.get_process_working_directory())
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if not process:
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self.fail("SBTarget.LaunchProcess() failed")
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import lldbsuite.test.lldbutil as lldbutil
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for thread in process:
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if thread.GetStopReason() == lldb.eStopReasonBreakpoint:
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for frame in thread:
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# Dump the registers of this frame using
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# lldbutil.get_GPRs() and friends.
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if self.TraceOn():
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print(frame)
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REGs = lldbutil.get_GPRs(frame)
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num = len(REGs)
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if self.TraceOn():
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print(
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"\nNumber of general purpose registers: %d" %
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num)
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for reg in REGs:
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self.assertTrue(reg)
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if self.TraceOn():
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print("%s => %s" % (reg.GetName(), reg.GetValue()))
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REGs = lldbutil.get_FPRs(frame)
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num = len(REGs)
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if self.TraceOn():
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print("\nNumber of floating point registers: %d" % num)
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for reg in REGs:
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self.assertTrue(reg)
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if self.TraceOn():
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print("%s => %s" % (reg.GetName(), reg.GetValue()))
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REGs = lldbutil.get_ESRs(frame)
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if self.platformIsDarwin():
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if self.getArchitecture() != 'armv7' and self.getArchitecture() != 'armv7k':
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num = len(REGs)
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if self.TraceOn():
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print(
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"\nNumber of exception state registers: %d" %
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num)
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for reg in REGs:
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self.assertTrue(reg)
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if self.TraceOn():
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print(
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"%s => %s" %
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(reg.GetName(), reg.GetValue()))
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else:
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self.assertIsNone(REGs)
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# And these should also work.
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for kind in ["General Purpose Registers",
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"Floating Point Registers"]:
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REGs = lldbutil.get_registers(frame, kind)
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self.assertTrue(REGs)
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REGs = lldbutil.get_registers(
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frame, "Exception State Registers")
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if self.platformIsDarwin():
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if self.getArchitecture() != 'armv7' and self.getArchitecture() != 'armv7k':
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self.assertIsNotNone(REGs)
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else:
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self.assertIsNone(REGs)
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# We've finished dumping the registers for frame #0.
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break
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