7bc8ad5849
This patch provides mitigation for CVE-2017-5715, Spectre variant two, which affects the P5600 and P6600. It implements the LLVM part of -mindirect-jump=hazard. It is _not_ enabled by default for the P5600. The migitation strategy suggested by MIPS for these processors is to use hazard barrier instructions. 'jalr.hb' and 'jr.hb' are hazard barrier variants of the 'jalr' and 'jr' instructions respectively. These instructions impede the execution of instruction stream until architecturally defined hazards (changes to the instruction stream, privileged registers which may affect execution) are cleared. These instructions in MIPS' designs are not speculated past. These instructions are used with the attribute +use-indirect-jump-hazard when branching indirectly and for indirect function calls. These instructions are defined by the MIPS32R2 ISA, so this mitigation method is not compatible with processors which implement an earlier revision of the MIPS ISA. Performance benchmarking of this option with -fpic and lld using -z hazardplt shows a difference of overall 10%~ time increase for the LLVM testsuite. Certain benchmarks such as methcall show a substantially larger increase in time due to their nature. Reviewers: atanasyan, zoran.jovanovic Differential Revision: https://reviews.llvm.org/D43486 llvm-svn: 325653
370 lines
7.4 KiB
TableGen
370 lines
7.4 KiB
TableGen
//===- MipsDSPInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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class DspMMRel;
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def Dsp2MicroMips : InstrMapping {
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let FilterClass = "DspMMRel";
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// Instructions with the same BaseOpcode and isNVStore values form a row.
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let RowFields = ["BaseOpcode"];
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// Instructions with the same predicate sense form a column.
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let ColFields = ["Arch"];
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// The key column is the unpredicated instructions.
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let KeyCol = ["dsp"];
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// Value columns are PredSense=true and PredSense=false
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let ValueCols = [["dsp"], ["mmdsp"]];
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}
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def HasDSP : Predicate<"Subtarget->hasDSP()">,
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AssemblerPredicate<"FeatureDSP">;
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def HasDSPR2 : Predicate<"Subtarget->hasDSPR2()">,
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AssemblerPredicate<"FeatureDSPR2">;
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def HasDSPR3 : Predicate<"Subtarget->hasDSPR3()">,
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AssemblerPredicate<"FeatureDSPR3">;
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class ISA_DSPR2 {
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list<Predicate> InsnPredicates = [HasDSPR2];
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}
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class ISA_DSPR3 {
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list<Predicate> InsnPredicates = [HasDSPR3];
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}
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// Fields.
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class Field6<bits<6> val> {
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bits<6> V = val;
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}
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def SPECIAL3_OPCODE : Field6<0b011111>;
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def REGIMM_OPCODE : Field6<0b000001>;
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class DSPInst<string opstr = "">
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: MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl {
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let InsnPredicates = [HasDSP];
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string BaseOpcode = opstr;
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string Arch = "dsp";
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}
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class PseudoDSP<dag outs, dag ins, list<dag> pattern,
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InstrItinClass itin = IIPseudo>
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: MipsPseudo<outs, ins, pattern, itin> {
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let InsnPredicates = [HasDSP];
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}
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class DSPInstAlias<string Asm, dag Result, bit Emit = 0b1>
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: InstAlias<Asm, Result, Emit>, PredicateControl {
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let InsnPredicates = [HasDSP];
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}
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// ADDU.QB sub-class format.
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class ADDU_QB_FMT<bits<5> op> : DSPInst {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b010000;
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}
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class RADDU_W_QB_FMT<bits<5> op> : DSPInst {
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bits<5> rd;
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bits<5> rs;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-16} = 0;
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let Inst{15-11} = rd;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b010000;
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}
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// CMPU.EQ.QB sub-class format.
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class CMP_EQ_QB_R2_FMT<bits<5> op> : DSPInst {
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bits<5> rs;
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bits<5> rt;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = 0;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b010001;
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}
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class CMP_EQ_QB_R3_FMT<bits<5> op> : DSPInst {
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bits<5> rs;
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bits<5> rt;
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bits<5> rd;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b010001;
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}
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class PRECR_SRA_PH_W_FMT<bits<5> op> : DSPInst {
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bits<5> rs;
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bits<5> rt;
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bits<5> sa;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = sa;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b010001;
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}
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// ABSQ_S.PH sub-class format.
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class ABSQ_S_PH_R2_FMT<bits<5> op> : DSPInst {
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bits<5> rd;
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bits<5> rt;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = 0;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b010010;
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}
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class REPL_FMT<bits<5> op> : DSPInst {
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bits<5> rd;
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bits<10> imm;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-16} = imm;
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let Inst{15-11} = rd;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b010010;
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}
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// SHLL.QB sub-class format.
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class SHLL_QB_FMT<bits<5> op> : DSPInst {
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bits<5> rd;
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bits<5> rt;
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bits<5> rs_sa;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs_sa;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b010011;
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}
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// LX sub-class format.
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class LX_FMT<bits<5> op> : DSPInst {
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bits<5> rd;
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bits<5> base;
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bits<5> index;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = base;
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let Inst{20-16} = index;
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let Inst{15-11} = rd;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b001010;
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}
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// ADDUH.QB sub-class format.
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class ADDUH_QB_FMT<bits<5> op> : DSPInst {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b011000;
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}
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// APPEND sub-class format.
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class APPEND_FMT<bits<5> op> : DSPInst {
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bits<5> rt;
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bits<5> rs;
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bits<5> sa;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = sa;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b110001;
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}
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// DPA.W.PH sub-class format.
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class DPA_W_PH_FMT<bits<5> op> : DSPInst {
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bits<2> ac;
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bits<5> rs;
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bits<5> rt;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-13} = 0;
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let Inst{12-11} = ac;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b110000;
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}
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// MULT sub-class format.
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class MULT_FMT<bits<6> opcode, bits<6> funct> : DSPInst {
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bits<2> ac;
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bits<5> rs;
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bits<5> rt;
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let Opcode = opcode;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-13} = 0;
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let Inst{12-11} = ac;
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let Inst{10-6} = 0;
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let Inst{5-0} = funct;
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}
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// MFHI sub-class format.
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class MFHI_FMT<bits<6> funct> : DSPInst {
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bits<5> rd;
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bits<2> ac;
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let Inst{31-26} = 0;
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let Inst{25-23} = 0;
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let Inst{22-21} = ac;
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let Inst{20-16} = 0;
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let Inst{15-11} = rd;
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let Inst{10-6} = 0;
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let Inst{5-0} = funct;
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}
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// MTHI sub-class format.
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class MTHI_FMT<bits<6> funct> : DSPInst {
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bits<5> rs;
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bits<2> ac;
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let Inst{31-26} = 0;
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let Inst{25-21} = rs;
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let Inst{20-13} = 0;
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let Inst{12-11} = ac;
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let Inst{10-6} = 0;
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let Inst{5-0} = funct;
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}
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// EXTR.W sub-class format (type 1).
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class EXTR_W_TY1_FMT<bits<5> op> : DSPInst {
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bits<5> rt;
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bits<2> ac;
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bits<5> shift_rs;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = shift_rs;
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let Inst{20-16} = rt;
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let Inst{15-13} = 0;
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let Inst{12-11} = ac;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b111000;
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}
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// SHILO sub-class format.
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class SHILO_R1_FMT<bits<5> op> : DSPInst {
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bits<2> ac;
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bits<6> shift;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-20} = shift;
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let Inst{19-13} = 0;
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let Inst{12-11} = ac;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b111000;
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}
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class SHILO_R2_FMT<bits<5> op> : DSPInst {
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bits<2> ac;
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bits<5> rs;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-13} = 0;
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let Inst{12-11} = ac;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b111000;
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}
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class RDDSP_FMT<bits<5> op> : DSPInst {
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bits<5> rd;
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bits<10> mask;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-16} = mask;
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let Inst{15-11} = rd;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b111000;
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}
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class WRDSP_FMT<bits<5> op> : DSPInst {
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bits<5> rs;
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bits<10> mask;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-11} = mask;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b111000;
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}
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class BPOSGE32_FMT<bits<5> op> : DSPInst {
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bits<16> offset;
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let Opcode = REGIMM_OPCODE.V;
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let Inst{25-21} = 0;
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let Inst{20-16} = op;
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let Inst{15-0} = offset;
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}
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// INSV sub-class format.
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class INSV_FMT<bits<6> op> : DSPInst {
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bits<5> rt;
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bits<5> rs;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-6} = 0;
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let Inst{5-0} = op;
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}
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